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| author | Tom Rini <trini@ti.com> | 2012-07-30 14:49:50 -0700 |
|---|---|---|
| committer | Albert ARIBAUD <albert.u.boot@aribaud.net> | 2012-09-01 14:58:13 +0200 |
| commit | d4898ea89684aa285cfb34fbab6831c28dc0ed33 (patch) | |
| tree | d7413e876f856972cb78e98b854f9fe9826d426e /arch/arm/cpu/armv7 | |
| parent | 318f27c98fc9c07df983d4214ef723331181e7db (diff) | |
| download | u-boot-imx-d4898ea89684aa285cfb34fbab6831c28dc0ed33.zip u-boot-imx-d4898ea89684aa285cfb34fbab6831c28dc0ed33.tar.gz u-boot-imx-d4898ea89684aa285cfb34fbab6831c28dc0ed33.tar.bz2 | |
am33xx: Add DDR3 (Micron MT41J128M16JT-125) timings and support
Signed-off-by: Tom Rini <trini@ti.com>
Diffstat (limited to 'arch/arm/cpu/armv7')
| -rw-r--r-- | arch/arm/cpu/armv7/am33xx/ddr.c | 2 | ||||
| -rw-r--r-- | arch/arm/cpu/armv7/am33xx/emif4.c | 41 |
2 files changed, 43 insertions, 0 deletions
diff --git a/arch/arm/cpu/armv7/am33xx/ddr.c b/arch/arm/cpu/armv7/am33xx/ddr.c index bceed81..cffd4ab 100644 --- a/arch/arm/cpu/armv7/am33xx/ddr.c +++ b/arch/arm/cpu/armv7/am33xx/ddr.c @@ -46,6 +46,8 @@ void config_sdram(const struct emif_regs *regs) { writel(regs->ref_ctrl, &emif_reg->emif_sdram_ref_ctrl); writel(regs->ref_ctrl, &emif_reg->emif_sdram_ref_ctrl_shdw); + if (regs->zq_config) + writel(regs->zq_config, &emif_reg->emif_zq_config); writel(regs->sdram_config, &emif_reg->emif_sdram_config); } diff --git a/arch/arm/cpu/armv7/am33xx/emif4.c b/arch/arm/cpu/armv7/am33xx/emif4.c index 171d764..b2d7c0d 100644 --- a/arch/arm/cpu/armv7/am33xx/emif4.c +++ b/arch/arm/cpu/armv7/am33xx/emif4.c @@ -87,6 +87,38 @@ static const struct emif_regs ddr2_emif_reg_data = { .emif_ddr_phy_ctlr_1 = DDR2_EMIF_READ_LATENCY, }; +static const struct ddr_data ddr3_data = { + .datardsratio0 = DDR3_RD_DQS, + .datawdsratio0 = DDR3_WR_DQS, + .datafwsratio0 = DDR3_PHY_FIFO_WE, + .datawrsratio0 = DDR3_PHY_WR_DATA, + .datadldiff0 = PHY_DLL_LOCK_DIFF, +}; + +static const struct cmd_control ddr3_cmd_ctrl_data = { + .cmd0csratio = DDR3_RATIO, + .cmd0dldiff = DDR3_DLL_LOCK_DIFF, + .cmd0iclkout = DDR3_INVERT_CLKOUT, + + .cmd1csratio = DDR3_RATIO, + .cmd1dldiff = DDR3_DLL_LOCK_DIFF, + .cmd1iclkout = DDR3_INVERT_CLKOUT, + + .cmd2csratio = DDR3_RATIO, + .cmd2dldiff = DDR3_DLL_LOCK_DIFF, + .cmd2iclkout = DDR3_INVERT_CLKOUT, +}; + +static struct emif_regs ddr3_emif_reg_data = { + .sdram_config = DDR3_EMIF_SDCFG, + .ref_ctrl = DDR3_EMIF_SDREF, + .sdram_tim1 = DDR3_EMIF_TIM1, + .sdram_tim2 = DDR3_EMIF_TIM2, + .sdram_tim3 = DDR3_EMIF_TIM3, + .zq_config = DDR3_ZQ_CFG, + .emif_ddr_phy_ctlr_1 = DDR3_EMIF_READ_LATENCY, +}; + static void config_vtp(void) { writel(readl(&vtpreg->vtp0ctrlreg) | VTP_CTRL_ENABLE, @@ -115,6 +147,15 @@ void config_ddr(short ddr_type) ddr_data = &ddr2_data; ioctrl_val = DDR2_IOCTRL_VALUE; emif_regs = &ddr2_emif_reg_data; + } else if (ddr_type == EMIF_REG_SDRAM_TYPE_DDR3) { + ddr_pll = 303; + cmd_ctrl_data = &ddr3_cmd_ctrl_data; + ddr_data = &ddr3_data; + ioctrl_val = DDR3_IOCTRL_VALUE; + emif_regs = &ddr3_emif_reg_data; + } else { + puts("Unknown memory type"); + hang(); } enable_emif_clocks(); |