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| author | Soren Brinkmann <soren.brinkmann@xilinx.com> | 2013-11-21 13:39:00 -0800 |
|---|---|---|
| committer | Michal Simek <michal.simek@xilinx.com> | 2014-02-19 09:41:21 +0100 |
| commit | 1cd46ed2d30a931a66400635f158b14861f2d3b4 (patch) | |
| tree | ee03e2c758c81e0cb325a8afb3b0db2779950600 /arch/arm/cpu/armv7 | |
| parent | 2826fd320cf364077ccc64e645af468adcbe567e (diff) | |
| download | u-boot-imx-1cd46ed2d30a931a66400635f158b14861f2d3b4.zip u-boot-imx-1cd46ed2d30a931a66400635f158b14861f2d3b4.tar.gz u-boot-imx-1cd46ed2d30a931a66400635f158b14861f2d3b4.tar.bz2 | |
net: zynq_gem: Move RCLK details out of driver
The GEM driver should not need to know about Zynq specific details of
RCLK related registers and bitfields in the SLCR. Move those details to
the slcr driver.
Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Diffstat (limited to 'arch/arm/cpu/armv7')
| -rw-r--r-- | arch/arm/cpu/armv7/zynq/slcr.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/arch/arm/cpu/armv7/zynq/slcr.c b/arch/arm/cpu/armv7/zynq/slcr.c index b4c11c3..6710d92 100644 --- a/arch/arm/cpu/armv7/zynq/slcr.c +++ b/arch/arm/cpu/armv7/zynq/slcr.c @@ -50,7 +50,7 @@ void zynq_slcr_cpu_reset(void) } /* Setup clk for network */ -void zynq_slcr_gem_clk_setup(u32 gem_id, u32 rclk, u32 clk) +void zynq_slcr_gem_clk_setup(u32 gem_id, u32 clk) { zynq_slcr_unlock(); @@ -63,12 +63,12 @@ void zynq_slcr_gem_clk_setup(u32 gem_id, u32 rclk, u32 clk) /* Set divisors for appropriate frequency in GEM_CLK_CTRL */ writel(clk, &slcr_base->gem1_clk_ctrl); /* Configure GEM_RCLK_CTRL */ - writel(rclk, &slcr_base->gem1_rclk_ctrl); + writel(1, &slcr_base->gem1_rclk_ctrl); } else { /* Set divisors for appropriate frequency in GEM_CLK_CTRL */ writel(clk, &slcr_base->gem0_clk_ctrl); /* Configure GEM_RCLK_CTRL */ - writel(rclk, &slcr_base->gem0_rclk_ctrl); + writel(1, &slcr_base->gem0_rclk_ctrl); } udelay(100000); out: |