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| author | Rajeshwari Shinde <rajeshwari.s@samsung.com> | 2012-07-03 20:02:58 +0000 |
|---|---|---|
| committer | Albert ARIBAUD <albert.u.boot@aribaud.net> | 2012-09-01 14:58:23 +0200 |
| commit | 10bc1a7f49b2efec3eddca18949d28ad053f40bb (patch) | |
| tree | 4cffef2e3598c26d5194befa20fd1f3e42cfc722 /arch/arm/cpu/armv7 | |
| parent | 6071bcaec1cbbdd2679f9abdd36dfe16114bc315 (diff) | |
| download | u-boot-imx-10bc1a7f49b2efec3eddca18949d28ad053f40bb.zip u-boot-imx-10bc1a7f49b2efec3eddca18949d28ad053f40bb.tar.gz u-boot-imx-10bc1a7f49b2efec3eddca18949d28ad053f40bb.tar.bz2 | |
EXYNOS5: CLOCK: Add BPLL support
This patch adds support for BPLL clock.
Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com>
Acked-by: Joonyoung Shim <jy0922.shim@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Diffstat (limited to 'arch/arm/cpu/armv7')
| -rw-r--r-- | arch/arm/cpu/armv7/exynos/clock.c | 28 |
1 files changed, 21 insertions, 7 deletions
diff --git a/arch/arm/cpu/armv7/exynos/clock.c b/arch/arm/cpu/armv7/exynos/clock.c index 366c35a..5b7e0ff 100644 --- a/arch/arm/cpu/armv7/exynos/clock.c +++ b/arch/arm/cpu/armv7/exynos/clock.c @@ -98,7 +98,7 @@ static unsigned long exynos5_get_pll_clk(int pllreg) struct exynos5_clock *clk = (struct exynos5_clock *)samsung_get_base_clock(); unsigned long r, m, p, s, k = 0, mask, fout; - unsigned int freq, pll_div2_sel, mpll_fout_sel; + unsigned int freq, pll_div2_sel, fout_sel; switch (pllreg) { case APLL: @@ -115,6 +115,9 @@ static unsigned long exynos5_get_pll_clk(int pllreg) r = readl(&clk->vpll_con0); k = readl(&clk->vpll_con1); break; + case BPLL: + r = readl(&clk->bpll_con0); + break; default: printf("Unsupported PLL (%d)\n", pllreg); return 0; @@ -125,8 +128,9 @@ static unsigned long exynos5_get_pll_clk(int pllreg) * MPLL_CON: MIDV [25:16] * EPLL_CON: MIDV [24:16] * VPLL_CON: MIDV [24:16] + * BPLL_CON: MIDV [25:16] */ - if (pllreg == APLL || pllreg == MPLL) + if (pllreg == APLL || pllreg == MPLL || pllreg == BPLL) mask = 0x3ff; else mask = 0x1ff; @@ -155,13 +159,23 @@ static unsigned long exynos5_get_pll_clk(int pllreg) fout = m * (freq / (p * (1 << (s - 1)))); } - /* According to the user manual, in EVT1 MPLL always gives + /* According to the user manual, in EVT1 MPLL and BPLL always gives * 1.6GHz clock, so divide by 2 to get 800MHz MPLL clock.*/ - if (pllreg == MPLL) { + if (pllreg == MPLL || pllreg == BPLL) { pll_div2_sel = readl(&clk->pll_div2_sel); - mpll_fout_sel = (pll_div2_sel >> MPLL_FOUT_SEL_SHIFT) - & MPLL_FOUT_SEL_MASK; - if (mpll_fout_sel == 0) + + switch (pllreg) { + case MPLL: + fout_sel = (pll_div2_sel >> MPLL_FOUT_SEL_SHIFT) + & MPLL_FOUT_SEL_MASK; + break; + case BPLL: + fout_sel = (pll_div2_sel >> BPLL_FOUT_SEL_SHIFT) + & BPLL_FOUT_SEL_MASK; + break; + } + + if (fout_sel == 0) fout /= 2; } |