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| author | Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> | 2014-08-08 08:44:02 +0900 |
|---|---|---|
| committer | Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> | 2014-10-09 14:45:03 +0900 |
| commit | 88982893c4d50692b80a2155146cda9e42266c6b (patch) | |
| tree | 6deabe404924ddcd958ea790c864185be77bbb33 /arch/arm/cpu/armv7 | |
| parent | 237faf095fb43abbed6e40266ef7efccc8b9308b (diff) | |
| download | u-boot-imx-88982893c4d50692b80a2155146cda9e42266c6b.zip u-boot-imx-88982893c4d50692b80a2155146cda9e42266c6b.tar.gz u-boot-imx-88982893c4d50692b80a2155146cda9e42266c6b.tar.bz2 | |
arm: rmobile: r8a7794: Skip initialize L2 cache
rmobile/lowlevel_init_ca15.S are common in r8a7790, r8a7791 and r8a7794 of
rmobile SoCs. The initialize L2 cache in lowlevel_init_ca15.S only needed
for Cortex-A15. The r8a7794 is Cortex-A7, not Cortex-A15.
This adds Skip to initialize L2 cache when r8a7794.
Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Diffstat (limited to 'arch/arm/cpu/armv7')
| -rw-r--r-- | arch/arm/cpu/armv7/rmobile/lowlevel_init_ca15.S | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/arch/arm/cpu/armv7/rmobile/lowlevel_init_ca15.S b/arch/arm/cpu/armv7/rmobile/lowlevel_init_ca15.S index 5820e1a..879e0e0 100644 --- a/arch/arm/cpu/armv7/rmobile/lowlevel_init_ca15.S +++ b/arch/arm/cpu/armv7/rmobile/lowlevel_init_ca15.S @@ -35,6 +35,13 @@ do_cpu_waiting: */ .align 4 do_lowlevel_init: + ldr r2, =0xFF000044 /* PRR */ + ldr r1, [r2] + and r1, r1, #0x7F00 + lsrs r1, r1, #8 + cmp r1, #0x4C /* 0x4C is ID of r8a7794 */ + beq _exit_init_l2_a15 + /* surpress wfe if ca15 */ tst r4, #4 mrceq p15, 0, r0, c1, c0, 1 /* actlr */ |