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author | Jaehoon Chung <jh80.chung@samsung.com> | 2011-05-17 21:19:17 +0000 |
---|---|---|
committer | Minkyu Kang <mk7.kang@samsung.com> | 2011-05-26 19:33:09 +0900 |
commit | 68a8cbfad93241387ee1385b9d19e3e2b7919c4e (patch) | |
tree | 0d7664d1ddf1e819f58d593815db7a61f0e2f25d /arch/arm/cpu/armv7 | |
parent | 5d845f2758d86f9287e2ac3d48fdcbe80ad1d21b (diff) | |
download | u-boot-imx-68a8cbfad93241387ee1385b9d19e3e2b7919c4e.zip u-boot-imx-68a8cbfad93241387ee1385b9d19e3e2b7919c4e.tar.gz u-boot-imx-68a8cbfad93241387ee1385b9d19e3e2b7919c4e.tar.bz2 |
S5P: add set_mmc_clk for external clock control
This patch added set_mmc_clk for external clock control.
c210 didn't support host clock control.
So We need external_clock_control function for c210.
Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Diffstat (limited to 'arch/arm/cpu/armv7')
-rw-r--r-- | arch/arm/cpu/armv7/s5pc1xx/clock.c | 5 | ||||
-rw-r--r-- | arch/arm/cpu/armv7/s5pc2xx/clock.c | 32 |
2 files changed, 37 insertions, 0 deletions
diff --git a/arch/arm/cpu/armv7/s5pc1xx/clock.c b/arch/arm/cpu/armv7/s5pc1xx/clock.c index e92647c..1c87e8f 100644 --- a/arch/arm/cpu/armv7/s5pc1xx/clock.c +++ b/arch/arm/cpu/armv7/s5pc1xx/clock.c @@ -336,3 +336,8 @@ unsigned long get_uart_clk(int dev_index) { return s5pc1xx_get_uart_clk(dev_index); } + +void set_mmc_clk(int dev_index, unsigned int div) +{ + /* Do NOTHING */ +} diff --git a/arch/arm/cpu/armv7/s5pc2xx/clock.c b/arch/arm/cpu/armv7/s5pc2xx/clock.c index 450a630..624de62 100644 --- a/arch/arm/cpu/armv7/s5pc2xx/clock.c +++ b/arch/arm/cpu/armv7/s5pc2xx/clock.c @@ -199,6 +199,33 @@ static unsigned long s5pc210_get_uart_clk(int dev_index) return uclk; } +/* s5pc210: set the mmc clock */ +static void s5pc210_set_mmc_clk(int dev_index, unsigned int div) +{ + struct s5pc210_clock *clk = + (struct s5pc210_clock *)samsung_get_base_clock(); + unsigned int addr; + unsigned int val; + + /* + * CLK_DIV_FSYS1 + * MMC0_PRE_RATIO [15:8], MMC1_PRE_RATIO [31:24] + * CLK_DIV_FSYS2 + * MMC2_PRE_RATIO [15:8], MMC3_PRE_RATIO [31:24] + */ + if (dev_index < 2) { + addr = (unsigned int)&clk->div_fsys1; + } else { + addr = (unsigned int)&clk->div_fsys2; + dev_index -= 2; + } + + val = readl(addr); + val &= ~(0xff << ((dev_index << 4) + 8)); + val |= (div & 0xff) << ((dev_index << 4) + 8); + writel(val, addr); +} + unsigned long get_pll_clk(int pllreg) { return s5pc210_get_pll_clk(pllreg); @@ -218,3 +245,8 @@ unsigned long get_uart_clk(int dev_index) { return s5pc210_get_uart_clk(dev_index); } + +void set_mmc_clk(int dev_index, unsigned int div) +{ + s5pc210_set_mmc_clk(dev_index, div); +} |