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| author | Benoît Thébaudeau <benoit.thebaudeau@advansee.com> | 2012-09-27 10:22:37 +0000 |
|---|---|---|
| committer | Tom Rini <trini@ti.com> | 2012-10-15 11:54:11 -0700 |
| commit | b94792982f8f5d584f4c032117ecbc8abcec977f (patch) | |
| tree | 379055bc5fc510e5b8bf4ffa3f9598f53d413d0b /arch/arm/cpu/armv7 | |
| parent | 649dc8abd9be85f6de441c3d4d2b7e0588156a38 (diff) | |
| download | u-boot-imx-b94792982f8f5d584f4c032117ecbc8abcec977f.zip u-boot-imx-b94792982f8f5d584f4c032117ecbc8abcec977f.tar.gz u-boot-imx-b94792982f8f5d584f4c032117ecbc8abcec977f.tar.bz2 | |
mx5 clocks: Fix get_lp_apm()
If CCM.CCSR.lp_apm is set, the lp_apm clock is not necessarily 32768 Hz x 1024.
In that case:
- on i.MX51, this clock comes from the output of the FPM,
- on i.MX53, this clock comes from the output of PLL4.
This patch fixes the code accordingly.
Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Stefano Babic <sbabic@denx.de>
Diffstat (limited to 'arch/arm/cpu/armv7')
| -rw-r--r-- | arch/arm/cpu/armv7/mx5/clock.c | 24 |
1 files changed, 23 insertions, 1 deletions
diff --git a/arch/arm/cpu/armv7/mx5/clock.c b/arch/arm/cpu/armv7/mx5/clock.c index fe0c0d3..8c71a51 100644 --- a/arch/arm/cpu/armv7/mx5/clock.c +++ b/arch/arm/cpu/armv7/mx5/clock.c @@ -221,6 +221,24 @@ static uint32_t decode_pll(struct mxc_pll_reg *pll, uint32_t infreq) return ret; } +#ifdef CONFIG_MX51 +/* + * This function returns the Frequency Pre-Multiplier clock. + */ +static u32 get_fpm(void) +{ + u32 mult; + u32 ccr = readl(&mxc_ccm->ccr); + + if (ccr & MXC_CCM_CCR_FPM_MULT) + mult = 1024; + else + mult = 512; + + return MXC_CLK32 * mult; +} +#endif + /* * Get mcu main rate */ @@ -326,7 +344,11 @@ static u32 get_lp_apm(void) u32 ccsr = readl(&mxc_ccm->ccsr); if (ccsr & MXC_CCM_CCSR_LP_APM) - ret_val = MXC_CLK32 * 1024; +#if defined(CONFIG_MX51) + ret_val = get_fpm(); +#elif defined(CONFIG_MX53) + ret_val = decode_pll(mxc_plls[PLL4_CLOCK], MXC_HCLK); +#endif else ret_val = MXC_HCLK; |