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| author | Benoît Thébaudeau <benoit.thebaudeau@advansee.com> | 2012-09-28 07:09:03 +0000 |
|---|---|---|
| committer | Tom Rini <trini@ti.com> | 2012-10-15 11:54:11 -0700 |
| commit | 414e1660c8e898539411d92fbacdefc3e6bfbdfb (patch) | |
| tree | c35c3c7ff2cc058ad105978707be0a1b089b8195 /arch/arm/cpu/armv7 | |
| parent | 248cdf0b5270651ca5eefb1aff4a338df6a1ca25 (diff) | |
| download | u-boot-imx-414e1660c8e898539411d92fbacdefc3e6bfbdfb.zip u-boot-imx-414e1660c8e898539411d92fbacdefc3e6bfbdfb.tar.gz u-boot-imx-414e1660c8e898539411d92fbacdefc3e6bfbdfb.tar.bz2 | |
mx51: Fix USB PHY clocks
The i.MX51 has a single USB PHY clock, while the i.MX53 has two. These 3 clocks
have different clock gate control bit-fields.
The existing code was correct only for i.MX53, so this patch fixes the i.MX51
use case.
Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Marek Vasut <marex@denx.de>
Cc: Jana Rapava <fermata7@gmail.com>
Cc: Wolfgang Grandegger <wg@denx.de>
Cc: Igor Grinberg <grinberg@compulab.co.il>
Diffstat (limited to 'arch/arm/cpu/armv7')
| -rw-r--r-- | arch/arm/cpu/armv7/mx5/clock.c | 25 |
1 files changed, 18 insertions, 7 deletions
diff --git a/arch/arm/cpu/armv7/mx5/clock.c b/arch/arm/cpu/armv7/mx5/clock.c index 171d762..4e10d81 100644 --- a/arch/arm/cpu/armv7/mx5/clock.c +++ b/arch/arm/cpu/armv7/mx5/clock.c @@ -126,23 +126,33 @@ int enable_i2c_clk(unsigned char enable, unsigned i2c_num) } #endif -void set_usb_phy1_clk(void) +void set_usb_phy_clk(void) { clrbits_le32(&mxc_ccm->cscmr1, MXC_CCM_CSCMR1_USB_PHY_CLK_SEL); } +#if defined(CONFIG_MX51) void enable_usb_phy1_clk(unsigned char enable) { unsigned int cg = enable ? MXC_CCM_CCGR_CG_ON : MXC_CCM_CCGR_CG_OFF; - clrsetbits_le32(&mxc_ccm->CCGR4, - MXC_CCM_CCGR4_USB_PHY1(MXC_CCM_CCGR_CG_MASK), - MXC_CCM_CCGR4_USB_PHY1(cg)); + clrsetbits_le32(&mxc_ccm->CCGR2, + MXC_CCM_CCGR2_USB_PHY(MXC_CCM_CCGR_CG_MASK), + MXC_CCM_CCGR2_USB_PHY(cg)); } -void set_usb_phy2_clk(void) +void enable_usb_phy2_clk(unsigned char enable) { - clrbits_le32(&mxc_ccm->cscmr1, MXC_CCM_CSCMR1_USB_PHY_CLK_SEL); + /* i.MX51 has a single USB PHY clock, so do nothing here. */ +} +#elif defined(CONFIG_MX53) +void enable_usb_phy1_clk(unsigned char enable) +{ + unsigned int cg = enable ? MXC_CCM_CCGR_CG_ON : MXC_CCM_CCGR_CG_OFF; + + clrsetbits_le32(&mxc_ccm->CCGR4, + MXC_CCM_CCGR4_USB_PHY1(MXC_CCM_CCGR_CG_MASK), + MXC_CCM_CCGR4_USB_PHY1(cg)); } void enable_usb_phy2_clk(unsigned char enable) @@ -153,6 +163,7 @@ void enable_usb_phy2_clk(unsigned char enable) MXC_CCM_CCGR4_USB_PHY2(MXC_CCM_CCGR_CG_MASK), MXC_CCM_CCGR4_USB_PHY2(cg)); } +#endif /* * Calculate the frequency of PLLn. @@ -804,7 +815,7 @@ void mxc_set_sata_internal_clock(void) u32 *tmp_base = (u32 *)(IIM_BASE_ADDR + 0x180c); - set_usb_phy1_clk(); + set_usb_phy_clk(); clrsetbits_le32(tmp_base, 0x6, 0x4); } |