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| author | Eric Nelson <eric.nelson@boundarydevices.com> | 2012-09-21 07:33:51 +0000 |
|---|---|---|
| committer | Tom Rini <trini@ti.com> | 2012-10-15 11:54:08 -0700 |
| commit | 0bb7e316f0ba1899ef2e94d75510c043683c212f (patch) | |
| tree | fa00e9103cf0a7e45ca6a826d16d36b18f276541 /arch/arm/cpu/armv7 | |
| parent | e72d617860f7833756acddaf09ac28a3d8986d4c (diff) | |
| download | u-boot-imx-0bb7e316f0ba1899ef2e94d75510c043683c212f.zip u-boot-imx-0bb7e316f0ba1899ef2e94d75510c043683c212f.tar.gz u-boot-imx-0bb7e316f0ba1899ef2e94d75510c043683c212f.tar.bz2 | |
i.MX6: provide functional names for CCM_CCGR0-CCGR6 bit fields
Add meaningful constants for each clock channels and use them for
enabling and disabling i.MX6 clocks.
Includes an update to enable/disable the IPU1 clock in
drivers/video/ipu_common to remove IMX5x register access
when used on i.MX6 as discussed in V1:
http://patchwork.ozlabs.org/patch/185129/
Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
Diffstat (limited to 'arch/arm/cpu/armv7')
| -rw-r--r-- | arch/arm/cpu/armv7/mx6/clock.c | 10 |
1 files changed, 6 insertions, 4 deletions
diff --git a/arch/arm/cpu/armv7/mx6/clock.c b/arch/arm/cpu/armv7/mx6/clock.c index fddb373..ed2c913 100644 --- a/arch/arm/cpu/armv7/mx6/clock.c +++ b/arch/arm/cpu/armv7/mx6/clock.c @@ -43,9 +43,9 @@ void enable_usboh3_clk(unsigned char enable) reg = __raw_readl(&imx_ccm->CCGR6); if (enable) - reg |= MXC_CCM_CCGR_CG_MASK << MXC_CCM_CCGR0_CG0_OFFSET; + reg |= MXC_CCM_CCGR6_USBOH3_MASK; else - reg &= ~(MXC_CCM_CCGR_CG_MASK << MXC_CCM_CCGR0_CG0_OFFSET); + reg &= ~(MXC_CCM_CCGR6_USBOH3_MASK); __raw_writel(reg, &imx_ccm->CCGR6); } @@ -59,7 +59,9 @@ int enable_i2c_clk(unsigned char enable, unsigned i2c_num) if (i2c_num > 2) return -EINVAL; - mask = MXC_CCM_CCGR_CG_MASK << ((i2c_num + 3) << 1); + + mask = MXC_CCM_CCGR_CG_MASK + << (MXC_CCM_CCGR2_I2C1_SERIAL_OFFSET + (i2c_num << 1)); reg = __raw_readl(&imx_ccm->CCGR2); if (enable) reg |= mask; @@ -321,7 +323,7 @@ int enable_sata_clock(void) /* Enable sata clock */ reg = readl(&imx_ccm->CCGR5); /* CCGR5 */ - reg |= MXC_CCM_CCGR5_CG2_MASK; + reg |= MXC_CCM_CCGR5_SATA_MASK; writel(reg, &imx_ccm->CCGR5); /* Enable PLLs */ |