summaryrefslogtreecommitdiff
path: root/arch/arm/cpu/armv7
diff options
context:
space:
mode:
authorFabio Estevam <fabio.estevam@freescale.com>2013-02-07 06:45:23 +0000
committerStefano Babic <sbabic@denx.de>2013-02-12 13:54:34 +0100
commit76c91e668a54a45fa06086d4044fcae0b6ce225a (patch)
treed67aadea25803bfb73fad2aded5ad09e30302715 /arch/arm/cpu/armv7
parent7c92c540754a0c3756d467a9b0695f2a40d1fe86 (diff)
downloadu-boot-imx-76c91e668a54a45fa06086d4044fcae0b6ce225a.zip
u-boot-imx-76c91e668a54a45fa06086d4044fcae0b6ce225a.tar.gz
u-boot-imx-76c91e668a54a45fa06086d4044fcae0b6ce225a.tar.bz2
mx6: Disable Power Down Bit of watchdog
On a mx6qsabresd revision C board with rev1.2 mx6q, the system gets resetted and it is not able to reach the Linux prompt. Comparing the watchdog behaviour on a revB versus revC board: - On a mx6qsabresd revB: U-Boot > reset resetting ... U-Boot 2013.01-10524-g432a3aa-dirty (Feb 07 2013 - 13:34:46) CPU: Freescale i.MX6Q rev1.1 at 792 MHz Reset cause: WDOG ... - On a mx6qsabresd revC: U-Boot > reset resetting ... U-Boot 2013.01-10524-g432a3aa-dirty (Feb 07 2013 - 13:34:46) CPU: Freescale i.MX6Q rev1.1 at 792 MHz Reset cause: POR So due to revC POR/watchdog circuitry whenever a watchdog occurs, it causes a POR. Clearing the PDE - Power Down Enable bit of WMCR registers fixes the problem and is also safe for all mx6 boards. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Otavio Salvador <otavio@ossystems.com.br> Acked-by: Stefano Babic <sbabic@denx.de>
Diffstat (limited to 'arch/arm/cpu/armv7')
-rw-r--r--arch/arm/cpu/armv7/mx6/soc.c12
1 files changed, 12 insertions, 0 deletions
diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c
index a8aad5d..efe4136 100644
--- a/arch/arm/cpu/armv7/mx6/soc.c
+++ b/arch/arm/cpu/armv7/mx6/soc.c
@@ -30,6 +30,7 @@
#include <asm/arch/clock.h>
#include <asm/arch/sys_proto.h>
#include <asm/imx-common/boot_mode.h>
+#include <stdbool.h>
struct scu_regs {
u32 ctrl;
@@ -121,12 +122,23 @@ void set_vddsoc(u32 mv)
writel(reg, &anatop->reg_core);
}
+static void imx_set_wdog_powerdown(bool enable)
+{
+ struct wdog_regs *wdog1 = (struct wdog_regs *)WDOG1_BASE_ADDR;
+ struct wdog_regs *wdog2 = (struct wdog_regs *)WDOG2_BASE_ADDR;
+
+ /* Write to the PDE (Power Down Enable) bit */
+ writew(enable, &wdog1->wmcr);
+ writew(enable, &wdog2->wmcr);
+}
+
int arch_cpu_init(void)
{
init_aips();
set_vddsoc(1200); /* Set VDDSOC to 1.2V */
+ imx_set_wdog_powerdown(false); /* Disable PDE bit of WMCR register */
return 0;
}