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| author | Hao Zhang <hzhang@ti.com> | 2014-10-22 16:32:30 +0300 |
|---|---|---|
| committer | Tom Rini <trini@ti.com> | 2014-10-23 11:27:05 -0400 |
| commit | bc45d5729fbec157370b826156cf45ce78471096 (patch) | |
| tree | 12c70e660d7dccfbff4fa2c798cdbb748b51871a /arch/arm/cpu/armv7 | |
| parent | 61d122583fb8163e0ea7c43a0fa7d5ff1241b782 (diff) | |
| download | u-boot-imx-bc45d5729fbec157370b826156cf45ce78471096.zip u-boot-imx-bc45d5729fbec157370b826156cf45ce78471096.tar.gz u-boot-imx-bc45d5729fbec157370b826156cf45ce78471096.tar.bz2 | |
keystone2: msmc: add MSMC cache coherency support for K2L SOC
This patch adds Keystone II Lamar (K2L) SoC specific definitions
to support MSMC cache coherency.
Acked-by: Vitaly Andrianov <vitalya@ti.com>
Signed-off-by: Hao Zhang <hzhang@ti.com>
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
Diffstat (limited to 'arch/arm/cpu/armv7')
| -rw-r--r-- | arch/arm/cpu/armv7/keystone/init.c | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/arch/arm/cpu/armv7/keystone/init.c b/arch/arm/cpu/armv7/keystone/init.c index a8f8aee..62081b7 100644 --- a/arch/arm/cpu/armv7/keystone/init.c +++ b/arch/arm/cpu/armv7/keystone/init.c @@ -25,12 +25,12 @@ int arch_cpu_init(void) chip_configuration_unlock(); icache_enable(); - msmc_share_all_segments(8); /* TETRIS */ - msmc_share_all_segments(9); /* NETCP */ - msmc_share_all_segments(10); /* QM PDSP */ - msmc_share_all_segments(11); /* PCIE 0 */ -#ifdef CONFIG_SOC_K2E - msmc_share_all_segments(13); /* PCIE 1 */ + msmc_share_all_segments(KS2_MSMC_SEGMENT_TETRIS); + msmc_share_all_segments(KS2_MSMC_SEGMENT_NETCP); + msmc_share_all_segments(KS2_MSMC_SEGMENT_QM_PDSP); + msmc_share_all_segments(KS2_MSMC_SEGMENT_PCIE0); +#if defined(CONFIG_SOC_K2E) || defined(CONFIG_SOC_K2L) + msmc_share_all_segments(KS2_MSMC_SEGMENT_PCIE1); #endif /* |