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authorDave Gerlach <d-gerlach@ti.com>2014-02-18 07:32:01 -0500
committerTom Rini <trini@ti.com>2014-03-04 09:42:07 -0500
commitb56b9a0884afab53f7c93cd3c90648437ca7e35e (patch)
tree483c584aa38656dd0ac9a11ab7beffe8d886ee5f /arch/arm/cpu/armv7
parentf84880f0f31e2d293b987d37446dc8a2e34aa925 (diff)
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ARM: AM43xx: Change DDR3 Reset Value
The bit DDR3_RST_DEF_VAL inside CTRL_DDR_IO represents the default value of the ddr reset value for DDR3 before the EMIF takes over. We must have this bit set high so that on exit from DeepSleep0 within the kernel the reset line has the proper value. Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
Diffstat (limited to 'arch/arm/cpu/armv7')
-rw-r--r--arch/arm/cpu/armv7/am33xx/emif4.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm/cpu/armv7/am33xx/emif4.c b/arch/arm/cpu/armv7/am33xx/emif4.c
index d28fceb..3e39752 100644
--- a/arch/arm/cpu/armv7/am33xx/emif4.c
+++ b/arch/arm/cpu/armv7/am33xx/emif4.c
@@ -113,7 +113,7 @@ void config_ddr(unsigned int pll, const struct ctrl_ioregs *ioregs,
writel(readl(&cm_device->cm_dll_ctrl) & ~0x1, &cm_device->cm_dll_ctrl);
while ((readl(&cm_device->cm_dll_ctrl) && CM_DLL_READYST) == 0)
;
- writel(0x0, &ddrctrl->ddrioctrl);
+ writel(0x80000000, &ddrctrl->ddrioctrl);
config_io_ctrl(ioregs);