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| author | Nishanth Menon <nm@ti.com> | 2015-03-09 17:12:00 -0500 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2015-03-13 09:28:48 -0400 |
| commit | b45c48a7c30734272371fede01e96f499a314664 (patch) | |
| tree | f419e13accf870c448e231c9702b656957767aef /arch/arm/cpu/armv7 | |
| parent | c616a0df297e886f09bf88523bcd03a86bdf8704 (diff) | |
| download | u-boot-imx-b45c48a7c30734272371fede01e96f499a314664.zip u-boot-imx-b45c48a7c30734272371fede01e96f499a314664.tar.gz u-boot-imx-b45c48a7c30734272371fede01e96f499a314664.tar.bz2 | |
ARM: Introduce erratum workaround for 454179
454179: Stale prediction may inhibit target address misprediction on
next predicted taken branch
Impacts: Every Cortex-A8 processors with revision lower than r2p1
Work around: Set IBE and disable branch size mispredict to 1
Also provide a hook for SoC specific handling to take place if needed.
Based on ARM errata Document revision 20.0 (13 Nov 2010)
Signed-off-by: Nishanth Menon <nm@ti.com>
Tested-by: Matt Porter <mporter@konsulko.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Diffstat (limited to 'arch/arm/cpu/armv7')
| -rw-r--r-- | arch/arm/cpu/armv7/cp15.c | 6 | ||||
| -rw-r--r-- | arch/arm/cpu/armv7/start.S | 13 |
2 files changed, 19 insertions, 0 deletions
diff --git a/arch/arm/cpu/armv7/cp15.c b/arch/arm/cpu/armv7/cp15.c index 8ac81c9..b44c9f9 100644 --- a/arch/arm/cpu/armv7/cp15.c +++ b/arch/arm/cpu/armv7/cp15.c @@ -21,3 +21,9 @@ void __weak v7_arch_cp15_set_l2aux_ctrl(u32 l2actlr, u32 cpu_midr, { asm volatile ("mcr p15, 1, %0, c15, c0, 0\n\t" : : "r"(l2actlr)); } + +void __weak v7_arch_cp15_set_acr(u32 acr, u32 cpu_midr, u32 cpu_rev_comb, + u32 cpu_variant, u32 cpu_rev) +{ + asm volatile ("mcr p15, 0, %0, c1, c0, 1\n\t" : : "r"(acr)); +} diff --git a/arch/arm/cpu/armv7/start.S b/arch/arm/cpu/armv7/start.S index 89637e2..8483687 100644 --- a/arch/arm/cpu/armv7/start.S +++ b/arch/arm/cpu/armv7/start.S @@ -189,6 +189,19 @@ ENTRY(cpu_init_cp15) skip_errata_798870: #endif +#ifdef CONFIG_ARM_ERRATA_454179 + cmp r2, #0x21 @ Only on < r2p1 + bge skip_errata_454179 + + mrc p15, 0, r0, c1, c0, 1 @ Read ACR + orr r0, r0, #(0x3 << 6) @ Set DBSM(BIT7) and IBE(BIT6) bits + push {r1-r5} @ Save the cpu info registers + bl v7_arch_cp15_set_acr + pop {r1-r5} @ Restore the cpu info - fall through + +skip_errata_454179: +#endif + mov pc, r5 @ back to my caller ENDPROC(cpu_init_cp15) |