diff options
author | Matt Porter <mporter@ti.com> | 2013-03-15 10:07:03 +0000 |
---|---|---|
committer | Tom Rini <trini@ti.com> | 2013-03-24 12:49:11 -0400 |
commit | 3ba65f97cbedb39fb486f42f8daa9b9e0d36705a (patch) | |
tree | 0349f033250c48a61c82a6c3bc5bf85ad220c6c1 /arch/arm/cpu/armv7 | |
parent | 81df2bab46d3bed319e21571c68db8e0a048bbfd (diff) | |
download | u-boot-imx-3ba65f97cbedb39fb486f42f8daa9b9e0d36705a.zip u-boot-imx-3ba65f97cbedb39fb486f42f8daa9b9e0d36705a.tar.gz u-boot-imx-3ba65f97cbedb39fb486f42f8daa9b9e0d36705a.tar.bz2 |
am33xx: refactor emif4/ddr to support multiple EMIF instances
The AM33xx emif4/ddr support closely matches what is need to support
TI814x except that TI814x has two EMIF instances. Refactor all the
emif4 helper calls and the config_ddr() init function to use an
additional instance number argument.
Signed-off-by: Matt Porter <mporter@ti.com>
Reviewed-by: Tom Rini <trini@ti.com>
Diffstat (limited to 'arch/arm/cpu/armv7')
-rw-r--r-- | arch/arm/cpu/armv7/am33xx/ddr.c | 107 | ||||
-rw-r--r-- | arch/arm/cpu/armv7/am33xx/emif4.c | 40 |
2 files changed, 85 insertions, 62 deletions
diff --git a/arch/arm/cpu/armv7/am33xx/ddr.c b/arch/arm/cpu/armv7/am33xx/ddr.c index 7932a39..d1e2fd3 100644 --- a/arch/arm/cpu/armv7/am33xx/ddr.c +++ b/arch/arm/cpu/armv7/am33xx/ddr.c @@ -24,15 +24,20 @@ http://www.ti.com/ /** * Base address for EMIF instances */ -static struct emif_reg_struct *emif_reg = { - (struct emif_reg_struct *)EMIF4_0_CFG_BASE}; +static struct emif_reg_struct *emif_reg[2] = { + (struct emif_reg_struct *)EMIF4_0_CFG_BASE, + (struct emif_reg_struct *)EMIF4_1_CFG_BASE}; /** - * Base address for DDR instance + * Base addresses for DDR PHY cmd/data regs */ -static struct ddr_regs *ddr_reg[2] = { - (struct ddr_regs *)DDR_PHY_BASE_ADDR, - (struct ddr_regs *)DDR_PHY_BASE_ADDR2}; +static struct ddr_cmd_regs *ddr_cmd_reg[2] = { + (struct ddr_cmd_regs *)DDR_PHY_CMD_ADDR, + (struct ddr_cmd_regs *)DDR_PHY_CMD_ADDR2}; + +static struct ddr_data_regs *ddr_data_reg[2] = { + (struct ddr_data_regs *)DDR_PHY_DATA_ADDR, + (struct ddr_data_regs *)DDR_PHY_DATA_ADDR2}; /** * Base address for ddr io control instances @@ -43,7 +48,7 @@ static struct ddr_cmdtctrl *ioctrl_reg = { /** * Configure SDRAM */ -void config_sdram(const struct emif_regs *regs) +void config_sdram(const struct emif_regs *regs, int nr) { if (regs->zq_config) { /* @@ -51,71 +56,85 @@ void config_sdram(const struct emif_regs *regs) * about 570us for a delay, which will be long enough * to configure things. */ - writel(0x2800, &emif_reg->emif_sdram_ref_ctrl); - writel(regs->zq_config, &emif_reg->emif_zq_config); + writel(0x2800, &emif_reg[nr]->emif_sdram_ref_ctrl); + writel(regs->zq_config, &emif_reg[nr]->emif_zq_config); writel(regs->sdram_config, &cstat->secure_emif_sdram_config); - writel(regs->sdram_config, &emif_reg->emif_sdram_config); - writel(regs->ref_ctrl, &emif_reg->emif_sdram_ref_ctrl); - writel(regs->ref_ctrl, &emif_reg->emif_sdram_ref_ctrl_shdw); + writel(regs->sdram_config, &emif_reg[nr]->emif_sdram_config); + writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl); + writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl_shdw); } - writel(regs->ref_ctrl, &emif_reg->emif_sdram_ref_ctrl); - writel(regs->ref_ctrl, &emif_reg->emif_sdram_ref_ctrl_shdw); - writel(regs->sdram_config, &emif_reg->emif_sdram_config); + writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl); + writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl_shdw); + writel(regs->sdram_config, &emif_reg[nr]->emif_sdram_config); } /** * Set SDRAM timings */ -void set_sdram_timings(const struct emif_regs *regs) +void set_sdram_timings(const struct emif_regs *regs, int nr) { - writel(regs->sdram_tim1, &emif_reg->emif_sdram_tim_1); - writel(regs->sdram_tim1, &emif_reg->emif_sdram_tim_1_shdw); - writel(regs->sdram_tim2, &emif_reg->emif_sdram_tim_2); - writel(regs->sdram_tim2, &emif_reg->emif_sdram_tim_2_shdw); - writel(regs->sdram_tim3, &emif_reg->emif_sdram_tim_3); - writel(regs->sdram_tim3, &emif_reg->emif_sdram_tim_3_shdw); + writel(regs->sdram_tim1, &emif_reg[nr]->emif_sdram_tim_1); + writel(regs->sdram_tim1, &emif_reg[nr]->emif_sdram_tim_1_shdw); + writel(regs->sdram_tim2, &emif_reg[nr]->emif_sdram_tim_2); + writel(regs->sdram_tim2, &emif_reg[nr]->emif_sdram_tim_2_shdw); + writel(regs->sdram_tim3, &emif_reg[nr]->emif_sdram_tim_3); + writel(regs->sdram_tim3, &emif_reg[nr]->emif_sdram_tim_3_shdw); } /** * Configure DDR PHY */ -void config_ddr_phy(const struct emif_regs *regs) +void config_ddr_phy(const struct emif_regs *regs, int nr) { - writel(regs->emif_ddr_phy_ctlr_1, &emif_reg->emif_ddr_phy_ctrl_1); - writel(regs->emif_ddr_phy_ctlr_1, &emif_reg->emif_ddr_phy_ctrl_1_shdw); + writel(regs->emif_ddr_phy_ctlr_1, + &emif_reg[nr]->emif_ddr_phy_ctrl_1); + writel(regs->emif_ddr_phy_ctlr_1, + &emif_reg[nr]->emif_ddr_phy_ctrl_1_shdw); } /** * Configure DDR CMD control registers */ -void config_cmd_ctrl(const struct cmd_control *cmd) +void config_cmd_ctrl(const struct cmd_control *cmd, int nr) { - writel(cmd->cmd0csratio, &ddr_reg[0]->cm0csratio); - writel(cmd->cmd0dldiff, &ddr_reg[0]->cm0dldiff); - writel(cmd->cmd0iclkout, &ddr_reg[0]->cm0iclkout); + writel(cmd->cmd0csratio, &ddr_cmd_reg[nr]->cm0csratio); + writel(cmd->cmd0dldiff, &ddr_cmd_reg[nr]->cm0dldiff); + writel(cmd->cmd0iclkout, &ddr_cmd_reg[nr]->cm0iclkout); - writel(cmd->cmd1csratio, &ddr_reg[0]->cm1csratio); - writel(cmd->cmd1dldiff, &ddr_reg[0]->cm1dldiff); - writel(cmd->cmd1iclkout, &ddr_reg[0]->cm1iclkout); + writel(cmd->cmd1csratio, &ddr_cmd_reg[nr]->cm1csratio); + writel(cmd->cmd1dldiff, &ddr_cmd_reg[nr]->cm1dldiff); + writel(cmd->cmd1iclkout, &ddr_cmd_reg[nr]->cm1iclkout); - writel(cmd->cmd2csratio, &ddr_reg[0]->cm2csratio); - writel(cmd->cmd2dldiff, &ddr_reg[0]->cm2dldiff); - writel(cmd->cmd2iclkout, &ddr_reg[0]->cm2iclkout); + writel(cmd->cmd2csratio, &ddr_cmd_reg[nr]->cm2csratio); + writel(cmd->cmd2dldiff, &ddr_cmd_reg[nr]->cm2dldiff); + writel(cmd->cmd2iclkout, &ddr_cmd_reg[nr]->cm2iclkout); } /** * Configure DDR DATA registers */ -void config_ddr_data(int macrono, const struct ddr_data *data) +void config_ddr_data(const struct ddr_data *data, int nr) { - writel(data->datardsratio0, &ddr_reg[macrono]->dt0rdsratio0); - writel(data->datawdsratio0, &ddr_reg[macrono]->dt0wdsratio0); - writel(data->datawiratio0, &ddr_reg[macrono]->dt0wiratio0); - writel(data->datagiratio0, &ddr_reg[macrono]->dt0giratio0); - writel(data->datafwsratio0, &ddr_reg[macrono]->dt0fwsratio0); - writel(data->datawrsratio0, &ddr_reg[macrono]->dt0wrsratio0); - writel(data->datauserank0delay, &ddr_reg[macrono]->dt0rdelays0); - writel(data->datadldiff0, &ddr_reg[macrono]->dt0dldiff0); + int i; + + for (i = 0; i < DDR_DATA_REGS_NR; i++) { + writel(data->datardsratio0, + &(ddr_data_reg[nr]+i)->dt0rdsratio0); + writel(data->datawdsratio0, + &(ddr_data_reg[nr]+i)->dt0wdsratio0); + writel(data->datawiratio0, + &(ddr_data_reg[nr]+i)->dt0wiratio0); + writel(data->datagiratio0, + &(ddr_data_reg[nr]+i)->dt0giratio0); + writel(data->datafwsratio0, + &(ddr_data_reg[nr]+i)->dt0fwsratio0); + writel(data->datawrsratio0, + &(ddr_data_reg[nr]+i)->dt0wrsratio0); + writel(data->datauserank0delay, + &(ddr_data_reg[nr]+i)->dt0rdelays0); + writel(data->datadldiff0, + &(ddr_data_reg[nr]+i)->dt0dldiff0); + } } void config_io_ctrl(unsigned long val) diff --git a/arch/arm/cpu/armv7/am33xx/emif4.c b/arch/arm/cpu/armv7/am33xx/emif4.c index 01e3a52..76459d8 100644 --- a/arch/arm/cpu/armv7/am33xx/emif4.c +++ b/arch/arm/cpu/armv7/am33xx/emif4.c @@ -44,44 +44,48 @@ void dram_init_banksize(void) #ifdef CONFIG_SPL_BUILD -static struct vtp_reg *vtpreg = (struct vtp_reg *)VTP0_CTRL_ADDR; +static struct vtp_reg *vtpreg[2] = { + (struct vtp_reg *)VTP0_CTRL_ADDR, + (struct vtp_reg *)VTP1_CTRL_ADDR}; +#ifdef CONFIG_AM33XX static struct ddr_ctrl *ddrctrl = (struct ddr_ctrl *)DDR_CTRL_ADDR; +#endif -static void config_vtp(void) +static void config_vtp(int nr) { - writel(readl(&vtpreg->vtp0ctrlreg) | VTP_CTRL_ENABLE, - &vtpreg->vtp0ctrlreg); - writel(readl(&vtpreg->vtp0ctrlreg) & (~VTP_CTRL_START_EN), - &vtpreg->vtp0ctrlreg); - writel(readl(&vtpreg->vtp0ctrlreg) | VTP_CTRL_START_EN, - &vtpreg->vtp0ctrlreg); + writel(readl(&vtpreg[nr]->vtp0ctrlreg) | VTP_CTRL_ENABLE, + &vtpreg[nr]->vtp0ctrlreg); + writel(readl(&vtpreg[nr]->vtp0ctrlreg) & (~VTP_CTRL_START_EN), + &vtpreg[nr]->vtp0ctrlreg); + writel(readl(&vtpreg[nr]->vtp0ctrlreg) | VTP_CTRL_START_EN, + &vtpreg[nr]->vtp0ctrlreg); /* Poll for READY */ - while ((readl(&vtpreg->vtp0ctrlreg) & VTP_CTRL_READY) != + while ((readl(&vtpreg[nr]->vtp0ctrlreg) & VTP_CTRL_READY) != VTP_CTRL_READY) ; } void config_ddr(unsigned int pll, unsigned int ioctrl, const struct ddr_data *data, const struct cmd_control *ctrl, - const struct emif_regs *regs) + const struct emif_regs *regs, int nr) { enable_emif_clocks(); ddr_pll_config(pll); - config_vtp(); - config_cmd_ctrl(ctrl); - - config_ddr_data(0, data); - config_ddr_data(1, data); + config_vtp(nr); + config_cmd_ctrl(ctrl, nr); + config_ddr_data(data, nr); +#ifdef CONFIG_AM33XX config_io_ctrl(ioctrl); /* Set CKE to be controlled by EMIF/DDR PHY */ writel(DDR_CKE_CTRL_NORMAL, &ddrctrl->ddrckectrl); +#endif /* Program EMIF instance */ - config_ddr_phy(regs); - set_sdram_timings(regs); - config_sdram(regs); + config_ddr_phy(regs, nr); + set_sdram_timings(regs, nr); + config_sdram(regs, nr); } #endif |