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authorBenoît Thébaudeau <benoit.thebaudeau@advansee.com>2012-09-27 10:23:58 +0000
committerTom Rini <trini@ti.com>2012-10-15 11:54:12 -0700
commitd5fe220df4afb7dda1aeeced3635f7f745723685 (patch)
tree2834ed8f2826155d88e4b835442653994e70152f /arch/arm/cpu/armv7
parent3cbd107b5f33364ef3ca286b2ffaffee79f14781 (diff)
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mx5 clocks: Fix MXC_FEC_CLK
The FEC clock does not come from PLL1, but from the IPG clock. The previous code was even inconsistent with itself, returning the IPG clock as expected for imx_get_fecclk(), but the PLL1 clock for mxc_get_clock(MXC_FEC_CLK). Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Cc: Stefano Babic <sbabic@denx.de>
Diffstat (limited to 'arch/arm/cpu/armv7')
-rw-r--r--arch/arm/cpu/armv7/mx5/clock.c5
1 files changed, 2 insertions, 3 deletions
diff --git a/arch/arm/cpu/armv7/mx5/clock.c b/arch/arm/cpu/armv7/mx5/clock.c
index dbfe87c..a59b88a 100644
--- a/arch/arm/cpu/armv7/mx5/clock.c
+++ b/arch/arm/cpu/armv7/mx5/clock.c
@@ -474,7 +474,7 @@ unsigned int mxc_get_clock(enum mxc_clock clk)
case MXC_CSPI_CLK:
return imx_get_cspiclk();
case MXC_FEC_CLK:
- return decode_pll(mxc_plls[PLL1_CLOCK], MXC_HCLK);
+ return get_ipg_clk();
case MXC_SATA_CLK:
return get_ahb_clk();
case MXC_DDR_CLK:
@@ -490,10 +490,9 @@ u32 imx_get_uartclk(void)
return get_uart_clk();
}
-
u32 imx_get_fecclk(void)
{
- return mxc_get_clock(MXC_IPG_CLK);
+ return get_ipg_clk();
}
static int gcd(int m, int n)