diff options
| author | Ye.Li <B37916@freescale.com> | 2014-06-10 18:16:52 +0800 |
|---|---|---|
| committer | Ye.Li <B37916@freescale.com> | 2014-06-17 11:13:54 +0800 |
| commit | bfcd6e5255bdf057835d9c78468015c65d1c953c (patch) | |
| tree | e0779cbae31a8f5bfe44959098e03e0808a56728 /arch/arm/cpu/armv7 | |
| parent | dd32db7e21d849e70958ef3584f7b2b0265f8289 (diff) | |
| download | u-boot-imx-bfcd6e5255bdf057835d9c78468015c65d1c953c.zip u-boot-imx-bfcd6e5255bdf057835d9c78468015c65d1c953c.tar.gz u-boot-imx-bfcd6e5255bdf057835d9c78468015c65d1c953c.tar.bz2 | |
ENGR00315894-51 iMX6SX: Add QuadSPI clock enable function
Enable the clock for QuadSPI controllers. Must be called at
initialization.
Signed-off-by: Ye.Li <B37916@freescale.com>
Diffstat (limited to 'arch/arm/cpu/armv7')
| -rw-r--r-- | arch/arm/cpu/armv7/mx6/clock.c | 42 |
1 files changed, 42 insertions, 0 deletions
diff --git a/arch/arm/cpu/armv7/mx6/clock.c b/arch/arm/cpu/armv7/mx6/clock.c index da8ba76..e3ca4f6 100644 --- a/arch/arm/cpu/armv7/mx6/clock.c +++ b/arch/arm/cpu/armv7/mx6/clock.c @@ -322,6 +322,48 @@ static u32 get_mmdc_ch0_clk(void) } #endif +#ifdef CONFIG_MX6SX +/* qspi_num can be from 0 - 1 */ +void enable_qspi_clk(int qspi_num) +{ + u32 reg = 0; + + /* Enable QuadSPI clock */ + switch (qspi_num) { + case 0: + reg = readl(&imx_ccm->CCGR3); + reg |= MXC_CCM_CCGR3_QSPI1_OFFSET; + writel(reg, &imx_ccm->CCGR3); + + /* set 50M : (50 = 396 / 2 / 4) */ + reg = readl(&imx_ccm->cscmr1); + reg &= ~(MXC_CCM_CSCMR1_QSPI1_PODF_MASK | + MXC_CCM_CSCMR1_QSPI1_CLK_SEL_MASK); + reg |= ((1 << MXC_CCM_CSCMR1_QSPI1_PODF_OFFSET) | + (2 << MXC_CCM_CSCMR1_QSPI1_CLK_SEL_OFFSET)); + writel(reg, &imx_ccm->cscmr1); + break; + case 1: + reg = readl(&imx_ccm->CCGR4); + reg |= MXC_CCM_CCGR4_QSPI2_ENFC_OFFSET; + writel(reg, &imx_ccm->CCGR4); + + /* set 50M : (50 = 396 / 2 / 4) */ + reg = readl(&imx_ccm->cs2cdr); + reg &= ~(MXC_CCM_CS2CDR_QSPI2_CLK_PODF_MASK | + MXC_CCM_CS2CDR_QSPI2_CLK_PRED_MASK | + MXC_CCM_CS2CDR_QSPI2_CLK_SEL_MASK); + reg |= (MXC_CCM_CS2CDR_QSPI2_CLK_PRED(0x1) | + MXC_CCM_CS2CDR_QSPI2_CLK_SEL(0x3)); + writel(reg, &imx_ccm->cs2cdr); + break; + default: + break; + + } +} +#endif + #ifdef CONFIG_FEC_MXC int enable_fec_anatop_clock(enum enet_freq freq) { |