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authorLokesh Vutla <lokeshvutla@ti.com>2013-12-10 15:02:23 +0530
committerTom Rini <trini@ti.com>2013-12-18 21:14:45 -0500
commitb5e01eecc89e3e5c2ed3c17b803529be3c3702fb (patch)
tree73824a5325ebcf7c0c7cfe28ac5790655f7ca2ca /arch/arm/cpu/armv7
parentd3daba10f159cca7e9d24c6f154926a9b92c75e3 (diff)
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ARM: AM43xx: GP_EVM: Add support for DDR3
GP EVM has 1GB DDR3 attached(Part no: MT41K512M8RH). Adding details for the same. Below is the brief description of DDR3 init sequence(SW leveling): -> Enable VTT regulator -> Configure VTP -> Configure DDR IO settings -> Disable initialization and refreshes until EMIF registers are programmed. -> Program Timing registers -> Program leveling registers -> Program PHY control and Temp alert and ZQ config registers. -> Enable initialization and refreshes and configure SDRAM CONFIG register Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Diffstat (limited to 'arch/arm/cpu/armv7')
-rw-r--r--arch/arm/cpu/armv7/am33xx/ddr.c6
-rw-r--r--arch/arm/cpu/armv7/omap-common/emif-common.c14
2 files changed, 4 insertions, 16 deletions
diff --git a/arch/arm/cpu/armv7/am33xx/ddr.c b/arch/arm/cpu/armv7/am33xx/ddr.c
index 1abbb07..d05e666 100644
--- a/arch/arm/cpu/armv7/am33xx/ddr.c
+++ b/arch/arm/cpu/armv7/am33xx/ddr.c
@@ -97,8 +97,10 @@ void config_sdram_emif4d5(const struct emif_regs *regs, int nr)
writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl);
writel(regs->sdram_config, &emif_reg[nr]->emif_sdram_config);
- configure_mr(nr, 0);
- configure_mr(nr, 1);
+ if (emif_sdram_type() == EMIF_SDRAM_TYPE_LPDDR2) {
+ configure_mr(nr, 0);
+ configure_mr(nr, 1);
+ }
}
/**
diff --git a/arch/arm/cpu/armv7/omap-common/emif-common.c b/arch/arm/cpu/armv7/omap-common/emif-common.c
index 5a3f285..cd6289b 100644
--- a/arch/arm/cpu/armv7/omap-common/emif-common.c
+++ b/arch/arm/cpu/armv7/omap-common/emif-common.c
@@ -50,20 +50,6 @@ inline u32 emif_num(u32 base)
return 0;
}
-/*
- * Get SDRAM type connected to EMIF.
- * Assuming similar SDRAM parts are connected to both EMIF's
- * which is typically the case. So it is sufficient to get
- * SDRAM type from EMIF1.
- */
-u32 emif_sdram_type()
-{
- struct emif_reg_struct *emif = (struct emif_reg_struct *)EMIF1_BASE;
-
- return (readl(&emif->emif_sdram_config) &
- EMIF_REG_SDRAM_TYPE_MASK) >> EMIF_REG_SDRAM_TYPE_SHIFT;
-}
-
static inline u32 get_mr(u32 base, u32 cs, u32 mr_addr)
{
u32 mr;