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| author | Ye.Li <B37916@freescale.com> | 2014-06-10 18:40:47 +0800 |
|---|---|---|
| committer | Ye.Li <B37916@freescale.com> | 2014-06-17 11:13:55 +0800 |
| commit | 3a6e8ad55fb8ccf09caa9e258e4b5aa21631c203 (patch) | |
| tree | e2e06f46eacccb3b44f106add90fb7d325c434ba /arch/arm/cpu/armv7 | |
| parent | 1d442553d0b201dc23e3ed0e0e434c2aa6f43d1f (diff) | |
| download | u-boot-imx-3a6e8ad55fb8ccf09caa9e258e4b5aa21631c203.zip u-boot-imx-3a6e8ad55fb8ccf09caa9e258e4b5aa21631c203.tar.gz u-boot-imx-3a6e8ad55fb8ccf09caa9e258e4b5aa21631c203.tar.bz2 | |
ENGR00315894-53 ENET:FEC Update fec_mxc driver for iMX6SX
1. iMX6SX enet rx have 64 bytes alignment limitation for DMA transfer.
For i.MX6SX platform, need to add below define in config file:
#define CONFIG_FEC_DMA_MINALIGN 64
2. Change to check READY bit in BD, not check the TDAR. On iMX6SX, FEC will
clear the TDAR prior than the READY bit of last BD. Since fec driver only
prepare two BD for transmit, this cause the BD send failed at the third
packet.
Signed-off-by: Fugang Duan <B38611@freescale.com>
Signed-off-by: Ye.Li <B37916@freescale.com>
Diffstat (limited to 'arch/arm/cpu/armv7')
0 files changed, 0 insertions, 0 deletions