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authorTom Rini <trini@ti.com>2012-07-30 14:13:56 -0700
committerAlbert ARIBAUD <albert.u.boot@aribaud.net>2012-09-01 14:58:13 +0200
commit318f27c98fc9c07df983d4214ef723331181e7db (patch)
treec7e365c7b76b894cbccdac74d7fa4ea98f20216b /arch/arm/cpu/armv7
parent942d3f0174700ec5d823f0f9a415b86d7cde2a9e (diff)
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am33xx: Rework config_ddr to make DDR3 support easier.
In order to support DDR3 as well as DDR2, we need to perform the same init sequence, but with different values. So change config_ddr() to toggle setting pointers/etc for what DDR2 wants, and then calling. Signed-off-by: Tom Rini <trini@ti.com>
Diffstat (limited to 'arch/arm/cpu/armv7')
-rw-r--r--arch/arm/cpu/armv7/am33xx/emif4.c37
1 files changed, 23 insertions, 14 deletions
diff --git a/arch/arm/cpu/armv7/am33xx/emif4.c b/arch/arm/cpu/armv7/am33xx/emif4.c
index abeebf2..171d764 100644
--- a/arch/arm/cpu/armv7/am33xx/emif4.c
+++ b/arch/arm/cpu/armv7/am33xx/emif4.c
@@ -104,26 +104,35 @@ static void config_vtp(void)
void config_ddr(short ddr_type)
{
- enable_emif_clocks();
+ int ddr_pll, ioctrl_val;
+ const struct emif_regs *emif_regs;
+ const struct ddr_data *ddr_data;
+ const struct cmd_control *cmd_ctrl_data;
if (ddr_type == EMIF_REG_SDRAM_TYPE_DDR2) {
- ddr_pll_config(266);
- config_vtp();
+ ddr_pll = 266;
+ cmd_ctrl_data = &ddr2_cmd_ctrl_data;
+ ddr_data = &ddr2_data;
+ ioctrl_val = DDR2_IOCTRL_VALUE;
+ emif_regs = &ddr2_emif_reg_data;
+ }
- config_cmd_ctrl(&ddr2_cmd_ctrl_data);
+ enable_emif_clocks();
+ ddr_pll_config(ddr_pll);
+ config_vtp();
+ config_cmd_ctrl(cmd_ctrl_data);
- config_ddr_data(0, &ddr2_data);
- config_ddr_data(1, &ddr2_data);
+ config_ddr_data(0, ddr_data);
+ config_ddr_data(1, ddr_data);
- config_io_ctrl(DDR2_IOCTRL_VALUE);
+ config_io_ctrl(ioctrl_val);
- /* Set CKE to be controlled by EMIF/DDR PHY */
- writel(DDR_CKE_CTRL_NORMAL, &ddrctrl->ddrckectrl);
+ /* Set CKE to be controlled by EMIF/DDR PHY */
+ writel(DDR_CKE_CTRL_NORMAL, &ddrctrl->ddrckectrl);
- /* Program EMIF instance */
- config_ddr_phy(&ddr2_emif_reg_data);
- set_sdram_timings(&ddr2_emif_reg_data);
- config_sdram(&ddr2_emif_reg_data);
- }
+ /* Program EMIF instance */
+ config_ddr_phy(emif_regs);
+ set_sdram_timings(emif_regs);
+ config_sdram(emif_regs);
}
#endif