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authorMichal Simek <michal.simek@xilinx.com>2014-05-15 09:40:14 +0200
committerMichal Simek <michal.simek@xilinx.com>2014-07-23 15:36:55 +0200
commit03606ff42eb11a6beacc766a78819561abe930b1 (patch)
tree059d01b50d56dc9ad77e6c4939a09e89a94409eb /arch/arm/cpu/armv7/zynq
parent2b25721645677de68ffdfd93dfa6fe5a8a389893 (diff)
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ARM: zynq: Show ECC status on the same line as DRAM size
Without this patch is DRAM size one line below DRAM: which is not nice Origin: I2C: ready DRAM: Memory: ECC disabled 1 GiB MMC: zynq_sdhci: 0 Fixed by this patch: I2C: ready DRAM: ECC disabled 1 GiB MMC: zynq_sdhci: 0 Signed-off-by: Michal Simek <michal.simek@xilinx.com> Tested-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Diffstat (limited to 'arch/arm/cpu/armv7/zynq')
-rw-r--r--arch/arm/cpu/armv7/zynq/ddrc.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/arm/cpu/armv7/zynq/ddrc.c b/arch/arm/cpu/armv7/zynq/ddrc.c
index e0ed3bf..1ea086d 100644
--- a/arch/arm/cpu/armv7/zynq/ddrc.c
+++ b/arch/arm/cpu/armv7/zynq/ddrc.c
@@ -34,7 +34,7 @@ void zynq_ddrc_init(void)
/* ECC is enabled when memory is in 16bit mode and it is enabled */
if ((ecctype == ZYNQ_DDRC_ECC_SCRUBREG_ECCMODE_SECDED) &&
(width == ZYNQ_DDRC_CTRLREG_BUSWIDTH_16BIT)) {
- puts("Memory: ECC enabled\n");
+ puts("ECC enabled ");
/*
* Clear the first 1MB because it is not initialized from
* first stage bootloader. To get ECC to work all memory has
@@ -42,6 +42,6 @@ void zynq_ddrc_init(void)
*/
memset((void *)0, 0, 1 * 1024 * 1024);
} else {
- puts("Memory: ECC disabled\n");
+ puts("ECC disabled ");
}
}