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author | Masahiro Yamada <yamada.m@jp.panasonic.com> | 2014-10-03 19:21:06 +0900 |
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committer | Masahiro Yamada <yamada.m@jp.panasonic.com> | 2014-10-05 14:10:09 +0900 |
commit | 5894ca007d217a2fa845facfbb62c6512396a145 (patch) | |
tree | 872971789f6bf682ff9fd9b0a0199ccd8f59febe /arch/arm/cpu/armv7/uniphier/ph1-ld4/bcu_init.c | |
parent | 7f368553fcada0b38e8a096fcba4fcd64e0d2020 (diff) | |
download | u-boot-imx-5894ca007d217a2fa845facfbb62c6512396a145.zip u-boot-imx-5894ca007d217a2fa845facfbb62c6512396a145.tar.gz u-boot-imx-5894ca007d217a2fa845facfbb62c6512396a145.tar.bz2 |
ARM: UniPhier: add UniPhier SoC support code
These are used by Panasonic UniPhier SoC family.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Diffstat (limited to 'arch/arm/cpu/armv7/uniphier/ph1-ld4/bcu_init.c')
-rw-r--r-- | arch/arm/cpu/armv7/uniphier/ph1-ld4/bcu_init.c | 33 |
1 files changed, 33 insertions, 0 deletions
diff --git a/arch/arm/cpu/armv7/uniphier/ph1-ld4/bcu_init.c b/arch/arm/cpu/armv7/uniphier/ph1-ld4/bcu_init.c new file mode 100644 index 0000000..85f37f2 --- /dev/null +++ b/arch/arm/cpu/armv7/uniphier/ph1-ld4/bcu_init.c @@ -0,0 +1,33 @@ +/* + * Copyright (C) 2011-2014 Panasonic Corporation + * Author: Masahiro Yamada <yamada.m@jp.panasonic.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/arch/bcu-regs.h> + +#define ch(x) ((x) >= 32 ? 0 : (x) < 0 ? 0x11111111 : 0x11111111 << (x)) + +void bcu_init(void) +{ + int shift; + + writel(0x44444444, BCSCR0); /* 0x20000000-0x3fffffff: ASM bus */ + writel(0x11111111, BCSCR2); /* 0x80000000-0x9fffffff: IPPC/IPPD-bus */ + writel(0x11111111, BCSCR3); /* 0xa0000000-0xbfffffff: IPPC/IPPD-bus */ + writel(0x11111111, BCSCR4); /* 0xc0000000-0xdfffffff: IPPC/IPPD-bus */ + writel(0x11111111, BCSCR5); /* 0xe0000000-0Xffffffff: IPPC/IPPD-bus */ + + /* Specify DDR channel */ + shift = (CONFIG_SDRAM1_BASE - CONFIG_SDRAM0_BASE) / 0x04000000 * 4; + writel(ch(shift), BCIPPCCHR2); /* 0x80000000-0x9fffffff */ + + shift -= 32; + writel(ch(shift), BCIPPCCHR3); /* 0xa0000000-0xbfffffff */ + + shift -= 32; + writel(ch(shift), BCIPPCCHR4); /* 0xc0000000-0xdfffffff */ +} |