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authorSimon Glass <sjg@chromium.org>2014-12-23 12:04:52 -0700
committerTom Rini <trini@ti.com>2015-01-16 14:52:52 -0500
commitf630974ccb3ce93e9607a3354e9acb266a8b7e95 (patch)
tree2252244c1709bd613d46dad9b5666b773b13de9f /arch/arm/cpu/armv7/sunxi
parent480ca13e74ddec62540079ddeb689cf275b3073f (diff)
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sunxi: Move SPL s_init() code to board_init_f()
The current sunxi implementation uses gdata, which is going away. It also sets up DRAM before board_init_f() in SPL. There is really no reason to do much in s_init() since board_init_f() is called immediately afterwards. The only change is that we need our own implementation of board_init_f() which sets up DRAM before the BSS (which is in DRAM) is cleared. The s_init() code runs once for SPL and again for U-Boot proper. We shouldn't need to init the clock/timer/gpio/i2c init twice, so just have it in SPL. Signed-off-by: Simon Glass <sjg@chromium.org>
Diffstat (limited to 'arch/arm/cpu/armv7/sunxi')
-rw-r--r--arch/arm/cpu/armv7/sunxi/board.c69
1 files changed, 37 insertions, 32 deletions
diff --git a/arch/arm/cpu/armv7/sunxi/board.c b/arch/arm/cpu/armv7/sunxi/board.c
index bc98c56..c4bea25 100644
--- a/arch/arm/cpu/armv7/sunxi/board.c
+++ b/arch/arm/cpu/armv7/sunxi/board.c
@@ -46,9 +46,8 @@ u32 spl_boot_mode(void)
{
return MMCSD_MODE_RAW;
}
-#endif
-int gpio_init(void)
+static int gpio_init(void)
{
#if CONFIG_CONS_INDEX == 1 && defined(CONFIG_UART0_PORT_F)
#if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I)
@@ -86,6 +85,42 @@ int gpio_init(void)
return 0;
}
+void board_init_f(ulong dummy)
+{
+#if defined CONFIG_MACH_SUN6I || defined CONFIG_MACH_SUN8I
+ /* Magic (undocmented) value taken from boot0, without this DRAM
+ * access gets messed up (seems cache related) */
+ setbits_le32(SUNXI_SRAMC_BASE + 0x44, 0x1800);
+#endif
+#if !defined CONFIG_SPL_BUILD && (defined CONFIG_MACH_SUN7I || \
+ defined CONFIG_MACH_SUN6I || defined CONFIG_MACH_SUN8I)
+ /* Enable SMP mode for CPU0, by setting bit 6 of Auxiliary Ctl reg */
+ asm volatile(
+ "mrc p15, 0, r0, c1, c0, 1\n"
+ "orr r0, r0, #1 << 6\n"
+ "mcr p15, 0, r0, c1, c0, 1\n");
+#endif
+
+ clock_init();
+ timer_init();
+ gpio_init();
+ i2c_init_board();
+
+ preloader_console_init();
+
+#ifdef CONFIG_SPL_I2C_SUPPORT
+ /* Needed early by sunxi_board_init if PMU is enabled */
+ i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
+#endif
+ sunxi_board_init();
+
+ /* Clear the BSS. */
+ memset(__bss_start, 0, __bss_end - __bss_start);
+
+ board_init_r(NULL, 0);
+}
+#endif
+
void reset_cpu(ulong addr)
{
#if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN5I) || defined(CONFIG_MACH_SUN7I)
@@ -114,36 +149,6 @@ void reset_cpu(ulong addr)
/* do some early init */
void s_init(void)
{
-#if defined CONFIG_SPL_BUILD && \
- (defined CONFIG_MACH_SUN6I || defined CONFIG_MACH_SUN8I)
- /* Magic (undocmented) value taken from boot0, without this DRAM
- * access gets messed up (seems cache related) */
- setbits_le32(SUNXI_SRAMC_BASE + 0x44, 0x1800);
-#endif
-#if !defined CONFIG_SPL_BUILD && (defined CONFIG_MACH_SUN7I || \
- defined CONFIG_MACH_SUN6I || defined CONFIG_MACH_SUN8I)
- /* Enable SMP mode for CPU0, by setting bit 6 of Auxiliary Ctl reg */
- asm volatile(
- "mrc p15, 0, r0, c1, c0, 1\n"
- "orr r0, r0, #1 << 6\n"
- "mcr p15, 0, r0, c1, c0, 1\n");
-#endif
-
- clock_init();
- timer_init();
- gpio_init();
- i2c_init_board();
-
-#ifdef CONFIG_SPL_BUILD
- gd = &gdata;
- preloader_console_init();
-
-#ifdef CONFIG_SPL_I2C_SUPPORT
- /* Needed early by sunxi_board_init if PMU is enabled */
- i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
-#endif
- sunxi_board_init();
-#endif
}
#ifndef CONFIG_SYS_DCACHE_OFF