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author | Aneesh V <aneesh@ti.com> | 2012-03-08 07:20:18 +0000 |
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committer | Albert ARIBAUD <albert.u.boot@aribaud.net> | 2012-05-15 08:31:26 +0200 |
commit | 74236acacc27168102b2e3fbcac3a80e5ed82fe4 (patch) | |
tree | d51b458bf87b6649851170c418bedb60ef1228d9 /arch/arm/cpu/armv7/s5pc1xx/cache.S | |
parent | 7245536d19aaf0a6dc1c2d4a8fa80adf2f2ae739 (diff) | |
download | u-boot-imx-74236acacc27168102b2e3fbcac3a80e5ed82fe4.zip u-boot-imx-74236acacc27168102b2e3fbcac3a80e5ed82fe4.tar.gz u-boot-imx-74236acacc27168102b2e3fbcac3a80e5ed82fe4.tar.bz2 |
armv7: add appropriate headers for assembly functions
Use ENTRY and ENDPROC with assembly functions to ensure
necessary assembler directives for all functions.
Signed-off-by: Aneesh V <aneesh@ti.com>
Acked-by: Mike Frysinger <vapier@gentoo.org>
Diffstat (limited to 'arch/arm/cpu/armv7/s5pc1xx/cache.S')
-rw-r--r-- | arch/arm/cpu/armv7/s5pc1xx/cache.S | 10 |
1 files changed, 6 insertions, 4 deletions
diff --git a/arch/arm/cpu/armv7/s5pc1xx/cache.S b/arch/arm/cpu/armv7/s5pc1xx/cache.S index c7d6221..000192c 100644 --- a/arch/arm/cpu/armv7/s5pc1xx/cache.S +++ b/arch/arm/cpu/armv7/s5pc1xx/cache.S @@ -25,20 +25,22 @@ .align 5 +#include <linux/linkage.h> + #ifndef CONFIG_SYS_L2CACHE_OFF -.global v7_outer_cache_enable -v7_outer_cache_enable: +ENTRY(v7_outer_cache_enable) push {r0, r1, r2, lr} mrc 15, 0, r3, cr1, cr0, 1 orr r3, r3, #2 mcr 15, 0, r3, cr1, cr0, 1 pop {r1, r2, r3, pc} +ENDPROC(v7_outer_cache_enable) -.global v7_outer_cache_disable -v7_outer_cache_disable: +ENTRY(v7_outer_cache_disable) push {r0, r1, r2, lr} mrc 15, 0, r3, cr1, cr0, 1 bic r3, r3, #2 mcr 15, 0, r3, cr1, cr0, 1 pop {r1, r2, r3, pc} +ENDPROC(v7_outer_cache_disable) #endif |