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| author | Simon Glass <sjg@chromium.org> | 2013-03-28 04:32:16 +0000 |
|---|---|---|
| committer | Minkyu Kang <mk7.kang@samsung.com> | 2013-04-01 14:02:08 +0900 |
| commit | 3d00c0cb96ff93a929700b80d89cb905e5ab5315 (patch) | |
| tree | 4e15549394ed5b4b6c30becec48ef2d0a928e604 /arch/arm/cpu/armv7/s5p-common/pwm.c | |
| parent | 4f3bfa97c4b8f88f44aa946427eb9be12b296c96 (diff) | |
| download | u-boot-imx-3d00c0cb96ff93a929700b80d89cb905e5ab5315.zip u-boot-imx-3d00c0cb96ff93a929700b80d89cb905e5ab5315.tar.gz u-boot-imx-3d00c0cb96ff93a929700b80d89cb905e5ab5315.tar.bz2 | |
Exynos: Change get_timer() to work correctly
At present get_timer() does not return sane values. It should count up
smoothly in milliscond intervals.
We can change the PWM to count down at 1MHz, providing a resolution
of 1us and a range of about an hour between required get_timer() calls.
Test with command "sf probe 1:0; time sf read 40008000 0 1000".
Try with different numbers of bytes and see that sane values are obtained
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Akshay Saraswat <akshay.s@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Diffstat (limited to 'arch/arm/cpu/armv7/s5p-common/pwm.c')
| -rw-r--r-- | arch/arm/cpu/armv7/s5p-common/pwm.c | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/arch/arm/cpu/armv7/s5p-common/pwm.c b/arch/arm/cpu/armv7/s5p-common/pwm.c index 44d7bc3..3147f59 100644 --- a/arch/arm/cpu/armv7/s5p-common/pwm.c +++ b/arch/arm/cpu/armv7/s5p-common/pwm.c @@ -174,6 +174,12 @@ int pwm_init(int pwm_id, int div, int invert) /* set count value */ offset = pwm_id * 3; + + /* + * TODO(sjg): Use this as a countdown timer for now. We count down + * from the maximum value to 0, then reset. + */ + timer_rate_hz = -1; writel(timer_rate_hz, &pwm->tcntb0 + offset); val = readl(&pwm->tcon) & ~(0xf << TCON_OFFSET(pwm_id)); |