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author | SRICHARAN R <r.sricharan@ti.com> | 2013-11-08 17:40:38 +0530 |
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committer | Tom Rini <trini@ti.com> | 2013-12-04 08:12:08 -0500 |
commit | 54d022e76c42d824315e28ea06c89c2452f98861 (patch) | |
tree | 7fd2255daf8be37b1a535c75358953fc7f4647a5 /arch/arm/cpu/armv7/omap4 | |
parent | 6c70935d7525a4b2b144b49457d2bae85f1d111a (diff) | |
download | u-boot-imx-54d022e76c42d824315e28ea06c89c2452f98861.zip u-boot-imx-54d022e76c42d824315e28ea06c89c2452f98861.tar.gz u-boot-imx-54d022e76c42d824315e28ea06c89c2452f98861.tar.bz2 |
ARM: DRA7/OMAP5: EMIF: Add workaround for bug 0039
When core power domain hits oswr, then DDR3 memories does not come back
while resuming. This is because when EMIF registers are lost, then the
controller takes care of copying the values from the shadow registers.
If the shadow registers are not updated with the right values, then this
results in incorrect settings while resuming. So updating the shadow registers
with the corresponding status registers here during the boot.
Signed-off-by: Sricharan R <r.sricharan@ti.com>
Diffstat (limited to 'arch/arm/cpu/armv7/omap4')
-rw-r--r-- | arch/arm/cpu/armv7/omap4/sdram_elpida.c | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/arch/arm/cpu/armv7/omap4/sdram_elpida.c b/arch/arm/cpu/armv7/omap4/sdram_elpida.c index e4c8316..811e776 100644 --- a/arch/arm/cpu/armv7/omap4/sdram_elpida.c +++ b/arch/arm/cpu/armv7/omap4/sdram_elpida.c @@ -321,3 +321,8 @@ void get_lpddr2_mr_regs(const struct lpddr2_mr_regs **regs) { *regs = &mr_regs; } + +__weak const struct read_write_regs *get_bug_regs(u32 *iterations) +{ + return 0; +} |