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| author | Heiko Schocher <hs@denx.de> | 2010-09-17 13:10:41 +0200 |
|---|---|---|
| committer | Wolfgang Denk <wd@denx.de> | 2010-09-19 19:29:53 +0200 |
| commit | 561142af20f1fd7b425d9425730014e656defb91 (patch) | |
| tree | 4b721c28e895b4067bd52186fa24b1f82b7cf72a /arch/arm/cpu/armv7/omap3 | |
| parent | e48b7c0aad687f0b42ba9985c3e2dc67c2cac71d (diff) | |
| download | u-boot-imx-561142af20f1fd7b425d9425730014e656defb91.zip u-boot-imx-561142af20f1fd7b425d9425730014e656defb91.tar.gz u-boot-imx-561142af20f1fd7b425d9425730014e656defb91.tar.bz2 | |
ARM: implement relocation for ARM V7 (OMAP)
Change the implementation for ARM V7 to relocate the code to an
arbitrary address in RAM.
Adapt the Beagle board (Cortex A8) to test the changes.
Portions of this work were supported by funding from
the CE Linux Forum.
Signed-off-by: Heiko Schocher <hs@denx.de>
Diffstat (limited to 'arch/arm/cpu/armv7/omap3')
| -rw-r--r-- | arch/arm/cpu/armv7/omap3/emif4.c | 34 | ||||
| -rw-r--r-- | arch/arm/cpu/armv7/omap3/sdrc.c | 38 |
2 files changed, 72 insertions, 0 deletions
diff --git a/arch/arm/cpu/armv7/omap3/emif4.c b/arch/arm/cpu/armv7/omap3/emif4.c index fae5b11..da2cd90 100644 --- a/arch/arm/cpu/armv7/omap3/emif4.c +++ b/arch/arm/cpu/armv7/omap3/emif4.c @@ -136,6 +136,7 @@ void do_emif4_init(void) * dram_init - * - Sets uboots idea of sdram size */ +#if defined(CONFIG_SYS_ARM_WITHOUT_RELOC) int dram_init(void) { DECLARE_GLOBAL_DATA_PTR; @@ -157,6 +158,39 @@ int dram_init(void) return 0; } +#else +int dram_init(void) +{ + DECLARE_GLOBAL_DATA_PTR; + unsigned int size0 = 0, size1 = 0; + + size0 = get_sdr_cs_size(CS0); + /* + * If a second bank of DDR is attached to CS1 this is + * where it can be started. Early init code will init + * memory on CS0. + */ + if ((sysinfo.mtype == DDR_COMBO) || (sysinfo.mtype == DDR_STACKED)) + size1 = get_sdr_cs_size(CS1); + + gd->ram_size = size0 + size1; + return 0; +} + +void dram_init_banksize (void) +{ + DECLARE_GLOBAL_DATA_PTR; + unsigned int size0 = 0, size1 = 0; + + size0 = get_sdr_cs_size(CS0); + size1 = get_sdr_cs_size(CS1); + + gd->bd->bi_dram[0].start = PHYS_SDRAM_1; + gd->bd->bi_dram[0].size = size0; + gd->bd->bi_dram[1].start = PHYS_SDRAM_1 + get_sdr_cs_offset(CS1); + gd->bd->bi_dram[1].size = size1; +} +#endif /* * mem_init() - diff --git a/arch/arm/cpu/armv7/omap3/sdrc.c b/arch/arm/cpu/armv7/omap3/sdrc.c index 8905224..2719bb5 100644 --- a/arch/arm/cpu/armv7/omap3/sdrc.c +++ b/arch/arm/cpu/armv7/omap3/sdrc.c @@ -163,6 +163,7 @@ void do_sdrc_init(u32 cs, u32 early) * dram_init - * - Sets uboots idea of sdram size */ +#if defined(CONFIG_SYS_ARM_WITHOUT_RELOC) int dram_init(void) { DECLARE_GLOBAL_DATA_PTR; @@ -188,6 +189,43 @@ int dram_init(void) return 0; } +#else +int dram_init(void) +{ + DECLARE_GLOBAL_DATA_PTR; + unsigned int size0 = 0, size1 = 0; + + size0 = get_sdr_cs_size(CS0); + /* + * If a second bank of DDR is attached to CS1 this is + * where it can be started. Early init code will init + * memory on CS0. + */ + if ((sysinfo.mtype == DDR_COMBO) || (sysinfo.mtype == DDR_STACKED)) { + do_sdrc_init(CS1, NOT_EARLY); + make_cs1_contiguous(); + + size1 = get_sdr_cs_size(CS1); + } + gd->ram_size = size0 + size1; + + return 0; +} + +void dram_init_banksize (void) +{ + DECLARE_GLOBAL_DATA_PTR; + unsigned int size0 = 0, size1 = 0; + + size0 = get_sdr_cs_size(CS0); + size1 = get_sdr_cs_size(CS1); + + gd->bd->bi_dram[0].start = PHYS_SDRAM_1; + gd->bd->bi_dram[0].size = size0; + gd->bd->bi_dram[1].start = PHYS_SDRAM_1 + get_sdr_cs_offset(CS1); + gd->bd->bi_dram[1].size = size1; +} +#endif /* * mem_init - |