diff options
| author | Albert ARIBAUD <albert.u.boot@aribaud.net> | 2013-08-10 19:03:59 +0200 |
|---|---|---|
| committer | Tom Rini <trini@ti.com> | 2013-08-28 11:44:58 -0400 |
| commit | 8d20836615eb7fa6330935a5f63e5cdd05cac7e5 (patch) | |
| tree | 77a5958ca98538506693ff37932a2dcd029e973c /arch/arm/cpu/armv7/omap3/lowlevel_init.S | |
| parent | e633ac019642689e3a2dd95bd644b3a10c7bbbb4 (diff) | |
| download | u-boot-imx-8d20836615eb7fa6330935a5f63e5cdd05cac7e5.zip u-boot-imx-8d20836615eb7fa6330935a5f63e5cdd05cac7e5.tar.gz u-boot-imx-8d20836615eb7fa6330935a5f63e5cdd05cac7e5.tar.bz2 | |
arm: omap3: fix SRAM copy and execution sequence
Fix size calculation in copy of go_to_speed into SRAM.
Use SRAM_CLK_CODE in call to SRAM-based go_to_speed.
Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
Diffstat (limited to 'arch/arm/cpu/armv7/omap3/lowlevel_init.S')
| -rw-r--r-- | arch/arm/cpu/armv7/omap3/lowlevel_init.S | 8 |
1 files changed, 3 insertions, 5 deletions
diff --git a/arch/arm/cpu/armv7/omap3/lowlevel_init.S b/arch/arm/cpu/armv7/omap3/lowlevel_init.S index 98c3c03..6f7261b 100644 --- a/arch/arm/cpu/armv7/omap3/lowlevel_init.S +++ b/arch/arm/cpu/armv7/omap3/lowlevel_init.S @@ -69,15 +69,13 @@ ENDPROC(do_omap3_emu_romcode_call) *************************************************************************/ ENTRY(cpy_clk_code) /* Copy DPLL code into SRAM */ - adr r0, go_to_speed /* get addr of clock setting code */ - mov r2, #384 /* r2 size to copy (div by 32 bytes) */ - mov r1, r1 /* r1 <- dest address (passed in) */ - add r2, r2, r0 /* r2 <- source end address */ + adr r0, go_to_speed /* copy from start of go_to_speed... */ + adr r2, lowlevel_init /* ... up to start of low_level_init */ next2: ldmia r0!, {r3 - r10} /* copy from source address [r0] */ stmia r1!, {r3 - r10} /* copy to target address [r1] */ cmp r0, r2 /* until source end address [r2] */ - bne next2 + blo next2 mov pc, lr /* back to caller */ ENDPROC(cpy_clk_code) |