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author | Ye.Li <B37916@freescale.com> | 2015-03-26 15:28:18 +0800 |
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committer | Peng Fan <Peng.Fan@freescale.com> | 2015-04-29 15:04:25 +0800 |
commit | 14a8e4e724a2c7fe918df06c49f661773458ed04 (patch) | |
tree | cd3273ed8854ff2558fe040adffb94d24412d227 /arch/arm/cpu/armv7/mx7/soc.c | |
parent | d6d1666c68edd93c1c1bc9b738850f6eeba01bdb (diff) | |
download | u-boot-imx-14a8e4e724a2c7fe918df06c49f661773458ed04.zip u-boot-imx-14a8e4e724a2c7fe918df06c49f661773458ed04.tar.gz u-boot-imx-14a8e4e724a2c7fe918df06c49f661773458ed04.tar.bz2 |
MLK-10477-1 imx: mx7d: Add QoS settings for EPDC
Add the QoS settings function which is used for EPDC
Signed-off-by: Ye.Li <B37916@freescale.com>
(cherry picked from commit 725a3bbbe0a172a0f4619d99bc198b9367b9fc5d)
Diffstat (limited to 'arch/arm/cpu/armv7/mx7/soc.c')
-rw-r--r-- | arch/arm/cpu/armv7/mx7/soc.c | 34 |
1 files changed, 34 insertions, 0 deletions
diff --git a/arch/arm/cpu/armv7/mx7/soc.c b/arch/arm/cpu/armv7/mx7/soc.c index d737f96..79a9909 100644 --- a/arch/arm/cpu/armv7/mx7/soc.c +++ b/arch/arm/cpu/armv7/mx7/soc.c @@ -121,6 +121,37 @@ static void imx_set_wdog_powerdown(bool enable) writew(enable, &wdog4->wmcr); } +#if defined(CONFIG_MXC_EPDC) +static void set_epdc_qos(void) +{ +#define REGS_QOS_BASE QOSC_IPS_BASE_ADDR +#define REGS_QOS_EPDC (QOSC_IPS_BASE_ADDR + 0x3400) +#define REGS_QOS_PXP0 (QOSC_IPS_BASE_ADDR + 0x2C00) +#define REGS_QOS_PXP1 (QOSC_IPS_BASE_ADDR + 0x3C00) + + writel(0, REGS_QOS_BASE); /* Disable clkgate & soft_reset */ + writel(0, REGS_QOS_BASE + 0x60); /* Enable all masters */ + writel(0, REGS_QOS_EPDC); /* Disable clkgate & soft_reset */ + writel(0, REGS_QOS_PXP0); /* Disable clkgate & soft_reset */ + writel(0, REGS_QOS_PXP1); /* Disable clkgate & soft_reset */ + + writel(0x0f020722, REGS_QOS_EPDC + 0xd0); /* WR, init = 7 with red flag */ + writel(0x0f020722, REGS_QOS_EPDC + 0xe0); /* RD, init = 7 with red flag */ + + writel(1, REGS_QOS_PXP0); /* OT_CTRL_EN =1 */ + writel(1, REGS_QOS_PXP1); /* OT_CTRL_EN =1 */ + + writel(0x0f020222, REGS_QOS_PXP0 + 0x50); /* WR, init = 2 with red flag */ + writel(0x0f020222, REGS_QOS_PXP1 + 0x50); /* WR, init = 2 with red flag */ + writel(0x0f020222, REGS_QOS_PXP0 + 0x60); /* rD, init = 2 with red flag */ + writel(0x0f020222, REGS_QOS_PXP1 + 0x60); /* rD, init = 2 with red flag */ + writel(0x0f020422, REGS_QOS_PXP0 + 0x70); /* tOTAL, init = 4 with red flag */ + writel(0x0f020422, REGS_QOS_PXP1 + 0x70); /* TOTAL, init = 4 with red flag */ + + writel(0xe080, IOMUXC_GPR_BASE_ADDR + 0x0034); /* EPDC AW/AR CACHE ENABLE */ +} +#endif + int arch_cpu_init(void) { init_aips(); @@ -135,6 +166,9 @@ int arch_cpu_init(void) mxs_dma_init(); #endif +#if defined(CONFIG_MXC_EPDC) + set_epdc_qos(); +#endif return 0; } |