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authorFabio Estevam <fabio.estevam@freescale.com>2013-12-26 14:51:31 -0200
committerStefano Babic <sbabic@denx.de>2014-01-02 17:16:50 +0100
commite113fd1972aa921258e3219e6666bc41c9459503 (patch)
tree9687424a10e73fe362ba72c04e2b9b7284245bce /arch/arm/cpu/armv7/mx6
parentfc740648bddbf1fdb26e6cba1a8b436a814ef8bc (diff)
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mx6: soc: Clear the LDO ramp values up prior to setting the LDO voltages
Since ROM may modify the LDO ramp up time according to fuse setting, it is safer to reset the ramp up field to its default value of 00: 00: 64 cycles of 24MHz clock; 01: 128 cycles of 24MHz clock; 02: 256 cycles of 24MHz clock; 03: 512 cycles of 24MHz clock; Signed-off-by: Anson Huang <b20788@freescale.com> Signed-off-by: Jason Liu <r64343@freescale.com> Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Diffstat (limited to 'arch/arm/cpu/armv7/mx6')
-rw-r--r--arch/arm/cpu/armv7/mx6/soc.c16
1 files changed, 16 insertions, 0 deletions
diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c
index 2eee6e9..486b870 100644
--- a/arch/arm/cpu/armv7/mx6/soc.c
+++ b/arch/arm/cpu/armv7/mx6/soc.c
@@ -93,6 +93,20 @@ void init_aips(void)
writel(0x00000000, &aips2->opacr4);
}
+static void clear_ldo_ramp(void)
+{
+ struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
+ int reg;
+
+ /* ROM may modify LDO ramp up time according to fuse setting, so in
+ * order to be in the safe side we neeed to reset these settings to
+ * match the reset value: 0'b00
+ */
+ reg = readl(&anatop->ana_misc2);
+ reg &= ~(0x3f << 24);
+ writel(reg, &anatop->ana_misc2);
+}
+
/*
* Set the VDDSOC
*
@@ -113,6 +127,8 @@ static void set_vddsoc(u32 mv)
else
val = (mv - 700) / 25;
+ clear_ldo_ramp();
+
/*
* Mask out the REG_CORE[22:18] bits (REG2_TRIG)
* and set them to the calculated value (0.7V + val * 0.25V)