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authorFabio Estevam <fabio.estevam@freescale.com>2013-09-13 00:36:28 -0300
committerStefano Babic <sbabic@denx.de>2013-09-20 17:55:37 +0200
commit31f07964c896e19b501e9a4a59a8df85515cd0b9 (patch)
tree2a0422e6df2908dbc65cfbe5fb11e92644252f15 /arch/arm/cpu/armv7/mx6
parent7df51fd8be413a6b831f0fa7b83cad76b5c4e951 (diff)
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mx6slevk: Add Ethernet support
mx6slevk has a SMSC8720 connected in RMII mode. Add support for it. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Diffstat (limited to 'arch/arm/cpu/armv7/mx6')
-rw-r--r--arch/arm/cpu/armv7/mx6/clock.c30
1 files changed, 30 insertions, 0 deletions
diff --git a/arch/arm/cpu/armv7/mx6/clock.c b/arch/arm/cpu/armv7/mx6/clock.c
index 7a29c9b..010d932 100644
--- a/arch/arm/cpu/armv7/mx6/clock.c
+++ b/arch/arm/cpu/armv7/mx6/clock.c
@@ -282,6 +282,36 @@ static u32 get_mmdc_ch0_clk(void)
return freq / (podf + 1);
}
+
+int enable_fec_anatop_clock(void)
+{
+ u32 reg = 0;
+ s32 timeout = 100000;
+
+ struct anatop_regs __iomem *anatop =
+ (struct anatop_regs __iomem *)ANATOP_BASE_ADDR;
+
+ reg = readl(&anatop->pll_enet);
+ if ((reg & BM_ANADIG_PLL_ENET_POWERDOWN) ||
+ (!(reg & BM_ANADIG_PLL_ENET_LOCK))) {
+ reg &= ~BM_ANADIG_PLL_ENET_POWERDOWN;
+ writel(reg, &anatop->pll_enet);
+ while (timeout--) {
+ if (readl(&anatop->pll_enet) & BM_ANADIG_PLL_ENET_LOCK)
+ break;
+ }
+ if (timeout < 0)
+ return -ETIMEDOUT;
+ }
+
+ /* Enable FEC clock */
+ reg |= BM_ANADIG_PLL_ENET_ENABLE;
+ reg &= ~BM_ANADIG_PLL_ENET_BYPASS;
+ writel(reg, &anatop->pll_enet);
+
+ return 0;
+}
+
#else
static u32 get_mmdc_ch0_clk(void)
{