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| author | Nitin Garg <nitin.garg@freescale.com> | 2014-05-27 12:11:43 -0500 |
|---|---|---|
| committer | Nitin Garg <nitin.garg@freescale.com> | 2014-05-27 22:17:02 -0500 |
| commit | d0912be964679ada052bcd07a03d4689e84dce2e (patch) | |
| tree | 65c87cd94547001c93d6d2a591b9eb6b7437d828 /arch/arm/cpu/armv7/mx6/soc.c | |
| parent | 748eac71fde78aa0c2e8cb3a3bab94bd994c06f5 (diff) | |
| download | u-boot-imx-d0912be964679ada052bcd07a03d4689e84dce2e.zip u-boot-imx-d0912be964679ada052bcd07a03d4689e84dce2e.tar.gz u-boot-imx-d0912be964679ada052bcd07a03d4689e84dce2e.tar.bz2 | |
ENGR00315499-6 ARM:imx6: Add USB gadget driver imx_udc to support Android fastboot
Android fastboot leans on the USB gadget driver to communicate with host. Porting
the imx_udc driver from v2009.08 with two changes: adding resource/memory release
APIs and replacing the uncached memory with cache flush&invalidate operations.
Pins and Clocks initialization are added to support boards:
mx6qdlsabresd, mx6qdlsabreauto, mx6slevk
Signed-off-by: Ye.Li <B37916@freescale.com>
Signed-off-by: Nitin Garg <nitin.garg@freescale.com>
Diffstat (limited to 'arch/arm/cpu/armv7/mx6/soc.c')
| -rw-r--r-- | arch/arm/cpu/armv7/mx6/soc.c | 50 |
1 files changed, 50 insertions, 0 deletions
diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c index 20ee264..a386e03 100644 --- a/arch/arm/cpu/armv7/mx6/soc.c +++ b/arch/arm/cpu/armv7/mx6/soc.c @@ -21,6 +21,10 @@ #include <stdbool.h> #include <asm/arch/mxc_hdmi.h> #include <asm/arch/crm_regs.h> +#ifdef CONFIG_IMX_UDC +#include <asm/arch/mx6_usbphy.h> +#include <usb/imx_udc.h> +#endif enum ldo_reg { LDO_ARM, @@ -653,3 +657,49 @@ void v7_outer_cache_disable(void) clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN); } #endif /* !CONFIG_SYS_L2CACHE_OFF */ + +#ifdef CONFIG_IMX_UDC +void set_usboh3_clk(void) +{ + udc_pins_setting(); +} + +void set_usb_phy1_clk(void) +{ + /* make sure pll3 is enable here */ + writel((BM_ANADIG_USB1_CHRG_DETECT_EN_B | + BM_ANADIG_USB1_CHRG_DETECT_CHK_CHRG_B), + ANATOP_BASE_ADDR + HW_ANADIG_USB1_CHRG_DETECT_SET); + + writel(BM_ANADIG_USB1_PLL_480_CTRL_EN_USB_CLKS, + ANATOP_BASE_ADDR + HW_ANADIG_USB1_PLL_480_CTRL_SET); +} +void enable_usb_phy1_clk(unsigned char enable) +{ + if (enable) + writel(BM_USBPHY_CTRL_CLKGATE, + USB_PHY0_BASE_ADDR + HW_USBPHY_CTRL_CLR); + else + writel(BM_USBPHY_CTRL_CLKGATE, + USB_PHY0_BASE_ADDR + HW_USBPHY_CTRL_SET); +} + +void reset_usb_phy1(void) +{ + /* Reset USBPHY module */ + u32 temp; + temp = readl(USB_PHY0_BASE_ADDR + HW_USBPHY_CTRL); + temp |= BM_USBPHY_CTRL_SFTRST; + writel(temp, USB_PHY0_BASE_ADDR + HW_USBPHY_CTRL); + udelay(10); + + /* Remove CLKGATE and SFTRST */ + temp = readl(USB_PHY0_BASE_ADDR + HW_USBPHY_CTRL); + temp &= ~(BM_USBPHY_CTRL_CLKGATE | BM_USBPHY_CTRL_SFTRST); + writel(temp, USB_PHY0_BASE_ADDR + HW_USBPHY_CTRL); + udelay(10); + + /* Power up the PHY */ + writel(0, USB_PHY0_BASE_ADDR + HW_USBPHY_PWD); +} +#endif |