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| author | Ye.Li <B37916@freescale.com> | 2014-06-16 15:21:16 +0800 |
|---|---|---|
| committer | Ye.Li <B37916@freescale.com> | 2014-06-17 11:13:41 +0800 |
| commit | b31a013148bf4b4b7cfec67c72a603e35f7bcb4f (patch) | |
| tree | e3765402c0163d5c2fc02145c183b566c4fd64df /arch/arm/cpu/armv7/mx6/soc.c | |
| parent | c89e63ce42c5da5fc0624589c1c9619af2e1eb1c (diff) | |
| download | u-boot-imx-b31a013148bf4b4b7cfec67c72a603e35f7bcb4f.zip u-boot-imx-b31a013148bf4b4b7cfec67c72a603e35f7bcb4f.tar.gz u-boot-imx-b31a013148bf4b4b7cfec67c72a603e35f7bcb4f.tar.bz2 | |
ENGR00315894-19 iMX6 Disable the L2 before chaning the PL310 latency
The Latency parameters of PL310 Tag RAM latency control register and
Data RAM Latency control register are set in L2 cache enable.
Setting these registers must have PL310 not enabled. But when using
Plugin mode boot, the PL310 is enabled by bootrom. Thus, disable
the PL310 before this setting.
Signed-off-by: Ye.Li <B37916@freescale.com>
Diffstat (limited to 'arch/arm/cpu/armv7/mx6/soc.c')
| -rw-r--r-- | arch/arm/cpu/armv7/mx6/soc.c | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c index c2edd5d..adc123f 100644 --- a/arch/arm/cpu/armv7/mx6/soc.c +++ b/arch/arm/cpu/armv7/mx6/soc.c @@ -708,6 +708,9 @@ void v7_outer_cache_enable(void) } #endif + /* Must disable the L2 before changing the latency parameters */ + clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN); + writel(0x132, &pl310->pl310_tag_latency_ctrl); writel(0x132, &pl310->pl310_data_latency_ctrl); |