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authorNitin Garg <nitin.garg@freescale.com>2014-05-28 19:55:43 -0500
committerNitin Garg <nitin.garg@freescale.com>2014-06-13 10:17:02 -0500
commit45d532a0237f5baf2ec95b4364ec5bc94d312689 (patch)
tree78aca68b08b41e2e183450cd7afb29958c4661c1 /arch/arm/cpu/armv7/mx6/soc.c
parent0b02843b18d3a2c5c8012c4248a5574a8f6998c7 (diff)
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ENGR00315499-21 HDMI: splash screen function enhancement
-Change HDMI video mode to VGA. -Add pixel clock fraction part setting in IPU driver, fix video mode timing issue. -Add overflow state clear workaround, fix kernel hang in HDMI driver issue. -Correct IPU clock to 264MHz. Signed-off-by: Sandor Yu <R01008@freescale.com> Signed-off-by: Nitin Garg <nitin.garg@freescale.com>
Diffstat (limited to 'arch/arm/cpu/armv7/mx6/soc.c')
-rw-r--r--arch/arm/cpu/armv7/mx6/soc.c12
1 files changed, 11 insertions, 1 deletions
diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c
index 0106385..99988e1 100644
--- a/arch/arm/cpu/armv7/mx6/soc.c
+++ b/arch/arm/cpu/armv7/mx6/soc.c
@@ -630,7 +630,8 @@ void imx_setup_hdmi(void)
{
struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
struct hdmi_regs *hdmi = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR;
- int reg;
+ int reg, count;
+ u8 val;
/* Turn on HDMI PHY clock */
reg = readl(&mxc_ccm->CCGR2);
@@ -647,6 +648,15 @@ void imx_setup_hdmi(void)
|(CHSCCDR_IPU_PRE_CLK_540M_PFD
<< MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_OFFSET);
writel(reg, &mxc_ccm->chsccdr);
+
+ /* Workaround to clear the overflow condition */
+ if (readb(&hdmi->ih_fc_stat2) & HDMI_IH_FC_STAT2_OVERFLOW_MASK) {
+ /* TMDS software reset */
+ writeb((u8)~HDMI_MC_SWRSTZ_TMDSSWRST_REQ, &hdmi->mc_swrstz);
+ val = readb(&hdmi->fc_invidconf);
+ for (count = 0 ; count < 5 ; count++)
+ writeb(val, &hdmi->fc_invidconf);
+ }
}
#endif