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| author | Peng Fan <Peng.Fan@freescale.com> | 2015-08-17 16:10:58 +0800 |
|---|---|---|
| committer | Stefano Babic <sbabic@denx.de> | 2015-09-02 15:34:12 +0200 |
| commit | 24139754f55e11a41bd90d0c8064a79228b573a3 (patch) | |
| tree | f057711d8346098ef528685cef8ee3e591fd04b4 /arch/arm/cpu/armv7/mx6/ddr.c | |
| parent | 43d9dc41368f236b042f63c9fbc01031f25612c1 (diff) | |
| download | u-boot-imx-24139754f55e11a41bd90d0c8064a79228b573a3.zip u-boot-imx-24139754f55e11a41bd90d0c8064a79228b573a3.tar.gz u-boot-imx-24139754f55e11a41bd90d0c8064a79228b573a3.tar.bz2 | |
imx: mx6: ddr no support MMDC1 for i.MX6SL
i.MX 6SoloLite only supports MMDC0, so do not access MMDC1 for i.MX 6SL.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Tim Harvey <tharvey@gateworks.com>
Reviewed-by: Stefano Babic <sbabic@denx.de>
Diffstat (limited to 'arch/arm/cpu/armv7/mx6/ddr.c')
| -rw-r--r-- | arch/arm/cpu/armv7/mx6/ddr.c | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/arch/arm/cpu/armv7/mx6/ddr.c b/arch/arm/cpu/armv7/mx6/ddr.c index b808627..28fa3cf 100644 --- a/arch/arm/cpu/armv7/mx6/ddr.c +++ b/arch/arm/cpu/armv7/mx6/ddr.c @@ -288,7 +288,8 @@ void mx6sdl_dram_iocfg(unsigned width, #define MR(val, ba, cmd, cs1) \ ((val << 16) | (1 << 15) | (cmd << 4) | (cs1 << 3) | ba) #define MMDC1(entry, value) do { \ - if (!is_cpu_type(MXC_CPU_MX6SX) && !is_cpu_type(MXC_CPU_MX6UL)) \ + if (!is_cpu_type(MXC_CPU_MX6SX) && !is_cpu_type(MXC_CPU_MX6UL) && \ + !is_cpu_type(MXC_CPU_MX6SL)) \ mmdc1->entry = value; \ } while (0) @@ -312,7 +313,8 @@ void mx6_dram_cfg(const struct mx6_ddr_sysinfo *sysinfo, u16 mem_speed = ddr3_cfg->mem_speed; mmdc0 = (struct mmdc_p_regs *)MMDC_P0_BASE_ADDR; - if (!is_cpu_type(MXC_CPU_MX6SX) && !is_cpu_type(MXC_CPU_MX6UL)) + if (!is_cpu_type(MXC_CPU_MX6SX) && !is_cpu_type(MXC_CPU_MX6UL) && + !is_cpu_type(MXC_CPU_MX6SL)) mmdc1 = (struct mmdc_p_regs *)MMDC_P1_BASE_ADDR; /* Limit mem_speed for MX6D/MX6Q */ |