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author | Tom Rini <trini@konsulko.com> | 2016-12-18 13:54:25 -0500 |
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committer | Tom Rini <trini@konsulko.com> | 2016-12-18 17:43:20 -0500 |
commit | 8ea05705a70135a94419b0d243666c1b51fe1f8d (patch) | |
tree | 495da728ccebe411445c144fb88ba35041db2096 /arch/arm/cpu/armv7/mx6/clock.c | |
parent | 0b4bc1b3ab1850fccbade3e6103f2036f6bdb364 (diff) | |
parent | 854bb75be98ad792ff64c26ae38a1392ea185cd6 (diff) | |
download | u-boot-imx-8ea05705a70135a94419b0d243666c1b51fe1f8d.zip u-boot-imx-8ea05705a70135a94419b0d243666c1b51fe1f8d.tar.gz u-boot-imx-8ea05705a70135a94419b0d243666c1b51fe1f8d.tar.bz2 |
Merge branch 'master' of git://www.denx.de/git/u-boot-imx
Migrate CONFIG_ARCH_USE_MEMSET/MEMCPY with this merge.
Signed-off-by: Tom Rini <trini@konsulko.com>
Diffstat (limited to 'arch/arm/cpu/armv7/mx6/clock.c')
-rw-r--r-- | arch/arm/cpu/armv7/mx6/clock.c | 143 |
1 files changed, 111 insertions, 32 deletions
diff --git a/arch/arm/cpu/armv7/mx6/clock.c b/arch/arm/cpu/armv7/mx6/clock.c index 2995628..fa54c95 100644 --- a/arch/arm/cpu/armv7/mx6/clock.c +++ b/arch/arm/cpu/armv7/mx6/clock.c @@ -171,6 +171,8 @@ int enable_i2c_clk(unsigned char enable, unsigned i2c_num) reg &= ~mask; __raw_writel(reg, &imx_ccm->CCGR2); } else { + if (is_mx6sll()) + return -EINVAL; if (is_mx6sx() || is_mx6ul() || is_mx6ull()) { mask = MXC_CCM_CCGR6_I2C4_MASK; addr = &imx_ccm->CCGR6; @@ -382,7 +384,7 @@ static u32 get_ipg_per_clk(void) u32 reg, perclk_podf; reg = __raw_readl(&imx_ccm->cscmr1); - if (is_mx6sl() || is_mx6sx() || + if (is_mx6sll() || is_mx6sl() || is_mx6sx() || is_mx6dqp() || is_mx6ul() || is_mx6ull()) { if (reg & MXC_CCM_CSCMR1_PER_CLK_SEL_MASK) return MXC_HCLK; /* OSC 24Mhz */ @@ -400,7 +402,7 @@ static u32 get_uart_clk(void) reg = __raw_readl(&imx_ccm->cscdr1); if (is_mx6sl() || is_mx6sx() || is_mx6dqp() || is_mx6ul() || - is_mx6ull()) { + is_mx6sll() || is_mx6ull()) { if (reg & MXC_CCM_CSCDR1_UART_CLK_SEL) freq = MXC_HCLK; } @@ -420,7 +422,7 @@ static u32 get_cspi_clk(void) MXC_CCM_CSCDR2_ECSPI_CLK_PODF_OFFSET; if (is_mx6dqp() || is_mx6sl() || is_mx6sx() || is_mx6ul() || - is_mx6ull()) { + is_mx6sll() || is_mx6ull()) { if (reg & MXC_CCM_CSCDR2_ECSPI_CLK_SEL_MASK) return MXC_HCLK / (cspi_podf + 1); } @@ -482,7 +484,8 @@ static u32 get_mmdc_ch0_clk(void) u32 freq, podf, per2_clk2_podf, pmu_misc2_audio_div; - if (is_mx6sx() || is_mx6ul() || is_mx6ull() || is_mx6sl()) { + if (is_mx6sx() || is_mx6ul() || is_mx6ull() || is_mx6sl() || + is_mx6sll()) { podf = (cbcdr & MXC_CCM_CBCDR_MMDC_CH1_PODF_MASK) >> MXC_CCM_CBCDR_MMDC_CH1_PODF_OFFSET; if (cbcdr & MXC_CCM_CBCDR_PERIPH2_CLK_SEL) { @@ -514,6 +517,11 @@ static u32 get_mmdc_ch0_clk(void) freq = mxc_get_pll_pfd(PLL_BUS, 0); break; case 3: + if (is_mx6sl()) { + freq = mxc_get_pll_pfd(PLL_BUS, 2) >> 1; + break; + } + pmu_misc2_audio_div = PMU_MISC2_AUDIO_DIV(__raw_readl(&imx_ccm->pmu_misc2)); switch (pmu_misc2_audio_div) { case 0: @@ -620,16 +628,19 @@ void mxs_set_lcdclk(u32 base_addr, u32 freq) debug("mxs_set_lcdclk, freq = %dKHz\n", freq); - if (!is_mx6sx() && !is_mx6ul() && !is_mx6ull()) { + if (!is_mx6sx() && !is_mx6ul() && !is_mx6ull() && !is_mx6sl() && + !is_mx6sll()) { debug("This chip not support lcd!\n"); return; } - if (base_addr == LCDIF1_BASE_ADDR) { - reg = readl(&imx_ccm->cscdr2); - /* Can't change clocks when clock not from pre-mux */ - if ((reg & MXC_CCM_CSCDR2_LCDIF1_CLK_SEL_MASK) != 0) - return; + if (!is_mx6sl()) { + if (base_addr == LCDIF1_BASE_ADDR) { + reg = readl(&imx_ccm->cscdr2); + /* Can't change clocks when clock not from pre-mux */ + if ((reg & MXC_CCM_CSCDR2_LCDIF1_CLK_SEL_MASK) != 0) + return; + } } if (is_mx6sx()) { @@ -700,24 +711,44 @@ void mxs_set_lcdclk(u32 base_addr, u32 freq) if (enable_pll_video(pll_div, pll_num, pll_denom, post_div)) return; - /* Select pre-lcd clock to PLL5 and set pre divider */ - clrsetbits_le32(&imx_ccm->cscdr2, - MXC_CCM_CSCDR2_LCDIF1_PRED_SEL_MASK | - MXC_CCM_CSCDR2_LCDIF1_PRE_DIV_MASK, - (0x2 << MXC_CCM_CSCDR2_LCDIF1_PRED_SEL_OFFSET) | - ((pred - 1) << - MXC_CCM_CSCDR2_LCDIF1_PRE_DIV_OFFSET)); + enable_lcdif_clock(base_addr, 0); + if (!is_mx6sl()) { + /* Select pre-lcd clock to PLL5 and set pre divider */ + clrsetbits_le32(&imx_ccm->cscdr2, + MXC_CCM_CSCDR2_LCDIF1_PRED_SEL_MASK | + MXC_CCM_CSCDR2_LCDIF1_PRE_DIV_MASK, + (0x2 << MXC_CCM_CSCDR2_LCDIF1_PRED_SEL_OFFSET) | + ((pred - 1) << + MXC_CCM_CSCDR2_LCDIF1_PRE_DIV_OFFSET)); + + /* Set the post divider */ + clrsetbits_le32(&imx_ccm->cbcmr, + MXC_CCM_CBCMR_LCDIF1_PODF_MASK, + ((postd - 1) << + MXC_CCM_CBCMR_LCDIF1_PODF_OFFSET)); + } else { + /* Select pre-lcd clock to PLL5 and set pre divider */ + clrsetbits_le32(&imx_ccm->cscdr2, + MXC_CCM_CSCDR2_LCDIF_PIX_CLK_SEL_MASK | + MXC_CCM_CSCDR2_LCDIF_PIX_PRE_DIV_MASK, + (0x2 << MXC_CCM_CSCDR2_LCDIF_PIX_CLK_SEL_OFFSET) | + ((pred - 1) << + MXC_CCM_CSCDR2_LCDIF_PIX_PRE_DIV_OFFSET)); + + /* Set the post divider */ + clrsetbits_le32(&imx_ccm->cscmr1, + MXC_CCM_CSCMR1_LCDIF_PIX_PODF_MASK, + (((postd - 1)^0x6) << + MXC_CCM_CSCMR1_LCDIF_PIX_PODF_OFFSET)); + } - /* Set the post divider */ - clrsetbits_le32(&imx_ccm->cbcmr, - MXC_CCM_CBCMR_LCDIF1_PODF_MASK, - ((postd - 1) << - MXC_CCM_CBCMR_LCDIF1_PODF_OFFSET)); + enable_lcdif_clock(base_addr, 1); } else if (is_mx6sx()) { /* Setting LCDIF2 for i.MX6SX */ if (enable_pll_video(pll_div, pll_num, pll_denom, post_div)) return; + enable_lcdif_clock(base_addr, 0); /* Select pre-lcd clock to PLL5 and set pre divider */ clrsetbits_le32(&imx_ccm->cscdr2, MXC_CCM_CSCDR2_LCDIF2_PRED_SEL_MASK | @@ -731,10 +762,12 @@ void mxs_set_lcdclk(u32 base_addr, u32 freq) MXC_CCM_CSCMR1_LCDIF2_PODF_MASK, ((postd - 1) << MXC_CCM_CSCMR1_LCDIF2_PODF_OFFSET)); + + enable_lcdif_clock(base_addr, 1); } } -int enable_lcdif_clock(u32 base_addr) +int enable_lcdif_clock(u32 base_addr, bool enable) { u32 reg = 0; u32 lcdif_clk_sel_mask, lcdif_ccgr3_mask; @@ -754,7 +787,7 @@ int enable_lcdif_clock(u32 base_addr) MXC_CCM_CCGR3_DISP_AXI_MASK) : (MXC_CCM_CCGR3_LCDIF1_PIX_MASK | MXC_CCM_CCGR3_DISP_AXI_MASK); - } else if (is_mx6ul() || is_mx6ull()) { + } else if (is_mx6ul() || is_mx6ull() || is_mx6sll()) { if (base_addr != LCDIF1_BASE_ADDR) { puts("Wrong LCD interface!\n"); return -EINVAL; @@ -762,23 +795,59 @@ int enable_lcdif_clock(u32 base_addr) /* Set to pre-mux clock at default */ lcdif_clk_sel_mask = MXC_CCM_CSCDR2_LCDIF1_CLK_SEL_MASK; lcdif_ccgr3_mask = MXC_CCM_CCGR3_LCDIF1_PIX_MASK; + } else if (is_mx6sl()) { + if (base_addr != LCDIF1_BASE_ADDR) { + puts("Wrong LCD interface!\n"); + return -EINVAL; + } + + reg = readl(&imx_ccm->CCGR3); + reg &= ~(MXC_CCM_CCGR3_LCDIF_AXI_MASK | + MXC_CCM_CCGR3_LCDIF_PIX_MASK); + writel(reg, &imx_ccm->CCGR3); + + if (enable) { + reg = readl(&imx_ccm->cscdr3); + reg &= ~MXC_CCM_CSCDR3_LCDIF_AXI_CLK_SEL_MASK; + reg |= 1 << MXC_CCM_CSCDR3_LCDIF_AXI_CLK_SEL_OFFSET; + writel(reg, &imx_ccm->cscdr3); + + reg = readl(&imx_ccm->CCGR3); + reg |= MXC_CCM_CCGR3_LCDIF_AXI_MASK | + MXC_CCM_CCGR3_LCDIF_PIX_MASK; + writel(reg, &imx_ccm->CCGR3); + } + + return 0; } else { return 0; } - reg = readl(&imx_ccm->cscdr2); - reg &= ~lcdif_clk_sel_mask; - writel(reg, &imx_ccm->cscdr2); - - /* Enable the LCDIF pix clock */ + /* Gate LCDIF clock first */ reg = readl(&imx_ccm->CCGR3); - reg |= lcdif_ccgr3_mask; + reg &= ~lcdif_ccgr3_mask; writel(reg, &imx_ccm->CCGR3); reg = readl(&imx_ccm->CCGR2); - reg |= MXC_CCM_CCGR2_LCD_MASK; + reg &= ~MXC_CCM_CCGR2_LCD_MASK; writel(reg, &imx_ccm->CCGR2); + if (enable) { + /* Select pre-mux */ + reg = readl(&imx_ccm->cscdr2); + reg &= ~lcdif_clk_sel_mask; + writel(reg, &imx_ccm->cscdr2); + + /* Enable the LCDIF pix clock */ + reg = readl(&imx_ccm->CCGR3); + reg |= lcdif_ccgr3_mask; + writel(reg, &imx_ccm->CCGR3); + + reg = readl(&imx_ccm->CCGR2); + reg |= MXC_CCM_CCGR2_LCD_MASK; + writel(reg, &imx_ccm->CCGR2); + } + return 0; } #endif @@ -916,6 +985,16 @@ static u32 get_usdhc_clk(u32 port) u32 cscmr1 = __raw_readl(&imx_ccm->cscmr1); u32 cscdr1 = __raw_readl(&imx_ccm->cscdr1); + if (is_mx6ul() || is_mx6ull()) { + if (port > 1) + return 0; + } + + if (is_mx6sll()) { + if (port > 2) + return 0; + } + switch (port) { case 0: usdhc_podf = (cscdr1 & MXC_CCM_CSCDR1_USDHC1_PODF_MASK) >> @@ -1079,7 +1158,7 @@ void hab_caam_clock_enable(unsigned char enable) { u32 reg; - if (is_mx6ull()) { + if (is_mx6ull() || is_mx6sll()) { /* CG5, DCP clock */ reg = __raw_readl(&imx_ccm->CCGR0); if (enable) |