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author | Tom Rini <trini@ti.com> | 2013-10-02 11:45:22 -0400 |
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committer | Tom Rini <trini@ti.com> | 2013-10-02 11:45:22 -0400 |
commit | 6297872cd5de4705b6318778261b1f3f64a34c11 (patch) | |
tree | 7159ac1b03daa6906c8609b2515e42214f3bc422 /arch/arm/cpu/armv7/mx6/clock.c | |
parent | 0ae39166b1babbc86da4269458da9bce198bce55 (diff) | |
parent | f04c53762962280365005c9db12ab561a18f2692 (diff) | |
download | u-boot-imx-6297872cd5de4705b6318778261b1f3f64a34c11.zip u-boot-imx-6297872cd5de4705b6318778261b1f3f64a34c11.tar.gz u-boot-imx-6297872cd5de4705b6318778261b1f3f64a34c11.tar.bz2 |
Merge branch 'master' of git://git.denx.de/u-boot-arm
Diffstat (limited to 'arch/arm/cpu/armv7/mx6/clock.c')
-rw-r--r-- | arch/arm/cpu/armv7/mx6/clock.c | 40 |
1 files changed, 35 insertions, 5 deletions
diff --git a/arch/arm/cpu/armv7/mx6/clock.c b/arch/arm/cpu/armv7/mx6/clock.c index 7efb0d2..df11678 100644 --- a/arch/arm/cpu/armv7/mx6/clock.c +++ b/arch/arm/cpu/armv7/mx6/clock.c @@ -228,13 +228,13 @@ static u32 get_axi_clk(void) static u32 get_emi_slow_clk(void) { - u32 emi_clk_sel, emi_slow_pof, cscmr1, root_freq = 0; + u32 emi_clk_sel, emi_slow_podf, cscmr1, root_freq = 0; cscmr1 = __raw_readl(&imx_ccm->cscmr1); emi_clk_sel = cscmr1 & MXC_CCM_CSCMR1_ACLK_EMI_SLOW_MASK; emi_clk_sel >>= MXC_CCM_CSCMR1_ACLK_EMI_SLOW_OFFSET; - emi_slow_pof = cscmr1 & MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_MASK; - emi_slow_pof >>= MXC_CCM_CSCMR1_ACLK_EMI_PODF_OFFSET; + emi_slow_podf = cscmr1 & MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_MASK; + emi_slow_podf >>= MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_OFFSET; switch (emi_clk_sel) { case 0: @@ -251,7 +251,7 @@ static u32 get_emi_slow_clk(void) break; } - return root_freq / (emi_slow_pof + 1); + return root_freq / (emi_slow_podf + 1); } #ifdef CONFIG_MX6SL @@ -282,6 +282,36 @@ static u32 get_mmdc_ch0_clk(void) return freq / (podf + 1); } + +int enable_fec_anatop_clock(void) +{ + u32 reg = 0; + s32 timeout = 100000; + + struct anatop_regs __iomem *anatop = + (struct anatop_regs __iomem *)ANATOP_BASE_ADDR; + + reg = readl(&anatop->pll_enet); + if ((reg & BM_ANADIG_PLL_ENET_POWERDOWN) || + (!(reg & BM_ANADIG_PLL_ENET_LOCK))) { + reg &= ~BM_ANADIG_PLL_ENET_POWERDOWN; + writel(reg, &anatop->pll_enet); + while (timeout--) { + if (readl(&anatop->pll_enet) & BM_ANADIG_PLL_ENET_LOCK) + break; + } + if (timeout < 0) + return -ETIMEDOUT; + } + + /* Enable FEC clock */ + reg |= BM_ANADIG_PLL_ENET_ENABLE; + reg &= ~BM_ANADIG_PLL_ENET_BYPASS; + writel(reg, &anatop->pll_enet); + + return 0; +} + #else static u32 get_mmdc_ch0_clk(void) { @@ -457,7 +487,7 @@ void enable_ipu_clock(void) struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; int reg; reg = readl(&mxc_ccm->CCGR3); - reg |= MXC_CCM_CCGR3_IPU1_IPU_DI0_OFFSET; + reg |= MXC_CCM_CCGR3_IPU1_IPU_MASK; writel(reg, &mxc_ccm->CCGR3); } /***************************************************/ |