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authorFabio Estevam <fabio.estevam@freescale.com>2012-05-07 10:56:00 +0000
committerStefano Babic <sbabic@denx.de>2012-10-17 18:25:12 +0200
commitc4fe17f6d83fa369af90be0764e82150c5879bd0 (patch)
treeb28894d2dfa41598b8bbf2159e05d662b9b54a85 /arch/arm/cpu/armv7/mx5
parentf5a289ba1ec0323bc588d504a5bb82a21f60cc0d (diff)
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mx5: Add workaround for ARM erratum ID 468414
Add the software workaround for ARM erratum ID 468414. According to mx53/mx51 errata document: "ENGcm11133 - ARM: NEON load data can be incorrectly forwarded to a subsequent request Description: Under very specific set of conditions, data from a Neon load request can be incorrectly forwarded to a subsequent, unrelated memory request. The conditions are as follows: • Neon loads and stores must be in use • Neon L1 caching must be disabled • Trustzone must be configured and in use • The secure memory address space and the non-secure memory address space both use the same physical addresses, either as an alias or the same memory location or for separate memory locations The issue is reported by ARM, erratum ID 468414, Category 2" Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Diffstat (limited to 'arch/arm/cpu/armv7/mx5')
-rw-r--r--arch/arm/cpu/armv7/mx5/lowlevel_init.S9
1 files changed, 9 insertions, 0 deletions
diff --git a/arch/arm/cpu/armv7/mx5/lowlevel_init.S b/arch/arm/cpu/armv7/mx5/lowlevel_init.S
index d62093b..29ec957 100644
--- a/arch/arm/cpu/armv7/mx5/lowlevel_init.S
+++ b/arch/arm/cpu/armv7/mx5/lowlevel_init.S
@@ -26,6 +26,13 @@
.section ".text.init", "x"
+.macro init_arm_erratum
+ /* ARM erratum ID #468414 */
+ mrc 15, 0, r1, c1, c0, 1
+ orr r1, r1, #(1 << 5) /* enable L1NEON bit */
+ mcr 15, 0, r1, c1, c0, 1
+.endm
+
/*
* L2CC Cache setup/invalidation/disable
*/
@@ -399,6 +406,8 @@ ENTRY(lowlevel_init)
str r1, [r0, #0x4]
#endif
+ init_arm_erratum
+
init_l2cc
init_aips