summaryrefslogtreecommitdiff
path: root/arch/arm/cpu/armv7/mx5
diff options
context:
space:
mode:
authorStefano Babic <sbabic@denx.de>2012-02-22 00:24:38 +0000
committerAlbert ARIBAUD <albert.u.boot@aribaud.net>2012-05-15 08:31:30 +0200
commit8c38b5d03d701134b7d6e4eeea94c229f7470d27 (patch)
treefb96f7388e249529720117180c28f83ad9207c76 /arch/arm/cpu/armv7/mx5
parent71cadda3ff8e0607c7b927582e1d9c9913857e6a (diff)
downloadu-boot-imx-8c38b5d03d701134b7d6e4eeea94c229f7470d27.zip
u-boot-imx-8c38b5d03d701134b7d6e4eeea94c229f7470d27.tar.gz
u-boot-imx-8c38b5d03d701134b7d6e4eeea94c229f7470d27.tar.bz2
MX53: add function to set SATA clock to internal
The MX53 SATA interface can use an internal clock (USB PHY1) instead of an external clock. This is an undocumented feature, but used on most Freescale's evaluation boards, such as MX53-loco. As stated by Freescale's support: Fuses (but not pins) may be used to configure SATA clocks. Particularly the i.MX53 Fuse_Map contains the next information about configuring SATA clocks : SATA_ALT_REF_CLK[1:0] (offset 0x180C) '00' - 100MHz (External) '01' - 50MHz (External) '10' - 120MHz, internal (USB PHY) '11' - Reserved Signed-off-by: Stefano Babic <sbabic@denx.de> CC: Fabio Estevam <fabio.estevam@freescale.com>
Diffstat (limited to 'arch/arm/cpu/armv7/mx5')
-rw-r--r--arch/arm/cpu/armv7/mx5/clock.c24
1 files changed, 24 insertions, 0 deletions
diff --git a/arch/arm/cpu/armv7/mx5/clock.c b/arch/arm/cpu/armv7/mx5/clock.c
index 8f8d01c..d769a4d 100644
--- a/arch/arm/cpu/armv7/mx5/clock.c
+++ b/arch/arm/cpu/armv7/mx5/clock.c
@@ -399,6 +399,30 @@ u32 imx_get_fecclk(void)
return mxc_get_clock(MXC_IPG_CLK);
}
+#ifdef CONFIG_MX53
+/*
+ * The clock for the external interface can be set to use internal clock
+ * if fuse bank 4, row 3, bit 2 is set.
+ * This is an undocumented feature and it was confirmed by Freescale's support:
+ * Fuses (but not pins) may be used to configure SATA clocks.
+ * Particularly the i.MX53 Fuse_Map contains the next information
+ * about configuring SATA clocks : SATA_ALT_REF_CLK[1:0] (offset 0x180C)
+ * '00' - 100MHz (External)
+ * '01' - 50MHz (External)
+ * '10' - 120MHz, internal (USB PHY)
+ * '11' - Reserved
+*/
+void mxc_set_sata_internal_clock(void)
+{
+ u32 *tmp_base =
+ (u32 *)(IIM_BASE_ADDR + 0x180c);
+
+ set_usb_phy1_clk();
+
+ writel((readl(tmp_base) & (~0x7)) | 0x4, tmp_base);
+}
+#endif
+
/*
* Dump some core clockes.
*/