diff options
author | Hao Zhang <hzhang@ti.com> | 2014-07-16 00:59:24 +0300 |
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committer | Tom Rini <trini@ti.com> | 2014-07-25 16:26:11 -0400 |
commit | 20187fd11c37226fac8661bbac96ddd4fdf507b1 (patch) | |
tree | a44f40207f8bc097ac8a3af82f1db40ea9b6ce14 /arch/arm/cpu/armv7/keystone/init.c | |
parent | 4dca7f0acc88708100a2b25b019befc9eea02f45 (diff) | |
download | u-boot-imx-20187fd11c37226fac8661bbac96ddd4fdf507b1.zip u-boot-imx-20187fd11c37226fac8661bbac96ddd4fdf507b1.tar.gz u-boot-imx-20187fd11c37226fac8661bbac96ddd4fdf507b1.tar.bz2 |
ARM: keystone2: add MSMC cache coherency support for K2E SOC
This patch adds Keystone2 K2E SOC specific code to support
MSMC cache coherency. Also create header file for msmc to hold
its API.
Acked-by: Murali Karicheri <m-karicheri2@ti.com>
Signed-off-by: Hao Zhang <hzhang@ti.com>
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
Diffstat (limited to 'arch/arm/cpu/armv7/keystone/init.c')
-rw-r--r-- | arch/arm/cpu/armv7/keystone/init.c | 12 |
1 files changed, 7 insertions, 5 deletions
diff --git a/arch/arm/cpu/armv7/keystone/init.c b/arch/arm/cpu/armv7/keystone/init.c index f4c293a..a8f8aee 100644 --- a/arch/arm/cpu/armv7/keystone/init.c +++ b/arch/arm/cpu/armv7/keystone/init.c @@ -10,6 +10,7 @@ #include <common.h> #include <ns16550.h> #include <asm/io.h> +#include <asm/arch/msmc.h> #include <asm/arch/clock.h> #include <asm/arch/hardware.h> @@ -24,11 +25,12 @@ int arch_cpu_init(void) chip_configuration_unlock(); icache_enable(); -#ifdef CONFIG_SOC_K2HK - share_all_segments(8); - share_all_segments(9); - share_all_segments(10); /* QM PDSP */ - share_all_segments(11); /* PCIE */ + msmc_share_all_segments(8); /* TETRIS */ + msmc_share_all_segments(9); /* NETCP */ + msmc_share_all_segments(10); /* QM PDSP */ + msmc_share_all_segments(11); /* PCIE 0 */ +#ifdef CONFIG_SOC_K2E + msmc_share_all_segments(13); /* PCIE 1 */ #endif /* |