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author | Aneesh V <aneesh@ti.com> | 2011-06-16 23:30:49 +0000 |
---|---|---|
committer | Albert ARIBAUD <albert.u.boot@aribaud.net> | 2011-07-04 10:55:25 +0200 |
commit | c2dd0d45540397704de9b13287417d21049d34c6 (patch) | |
tree | 1fa1e0a14c4061d1090596d227ea4f516d5e483a /arch/arm/cpu/armv7/cpu.c | |
parent | e47f2db5371047eb9bcd115fee084e6a8a92a239 (diff) | |
download | u-boot-imx-c2dd0d45540397704de9b13287417d21049d34c6.zip u-boot-imx-c2dd0d45540397704de9b13287417d21049d34c6.tar.gz u-boot-imx-c2dd0d45540397704de9b13287417d21049d34c6.tar.bz2 |
armv7: integrate cache maintenance support
- Enable I-cache on bootup
- Enable MMU and D-cache immediately after relocation
- Do necessary initialization before enabling d-cache and MMU
- Changes to cleanup_before_linux()
- Make changes according to the new framework
Signed-off-by: Aneesh V <aneesh@ti.com>
Diffstat (limited to 'arch/arm/cpu/armv7/cpu.c')
-rw-r--r-- | arch/arm/cpu/armv7/cpu.c | 47 |
1 files changed, 21 insertions, 26 deletions
diff --git a/arch/arm/cpu/armv7/cpu.c b/arch/arm/cpu/armv7/cpu.c index bc4238f..def9ced 100644 --- a/arch/arm/cpu/armv7/cpu.c +++ b/arch/arm/cpu/armv7/cpu.c @@ -35,13 +35,10 @@ #include <command.h> #include <asm/system.h> #include <asm/cache.h> - -static void cache_flush(void); +#include <asm/armv7.h> int cleanup_before_linux(void) { - unsigned int i; - /* * this function is called just before we call linux * it prepares the processor for linux @@ -50,31 +47,29 @@ int cleanup_before_linux(void) */ disable_interrupts(); - /* turn off I/D-cache */ + /* + * Turn off I-cache and invalidate it + */ icache_disable(); - dcache_disable(); - - /* invalidate I-cache */ - cache_flush(); + invalidate_icache_all(); -#ifndef CONFIG_L2_OFF - /* turn off L2 cache */ - l2_cache_disable(); - /* invalidate L2 cache also */ - invalidate_dcache(get_device_type()); -#endif - i = 0; - /* mem barrier to sync up things */ - asm("mcr p15, 0, %0, c7, c10, 4": :"r"(i)); + /* + * turn off D-cache + * dcache_disable() in turn flushes the d-cache and disables MMU + */ + dcache_disable(); -#ifndef CONFIG_L2_OFF - l2_cache_enable(); -#endif + /* + * After D-cache is flushed and before it is disabled there may + * be some new valid entries brought into the cache. We are sure + * that these lines are not dirty and will not affect our execution. + * (because unwinding the call-stack and setting a bit in CP15 SCTRL + * is all we did during this. We have not pushed anything on to the + * stack. Neither have we affected any static data) + * So just invalidate the entire d-cache again to avoid coherency + * problems for kernel + */ + invalidate_dcache_all(); return 0; } - -static void cache_flush(void) -{ - asm ("mcr p15, 0, %0, c7, c5, 0": :"r" (0)); -} |