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authorCooper Jr., Franklin <fcooper@ti.com>2014-06-27 13:31:15 -0500
committerTom Rini <trini@ti.com>2014-07-07 19:42:34 -0400
commit8038b497e742af2845523ed09b560bfc8cb42089 (patch)
treebaafb8646191200cd64ad7e49faabd77b7d6fe58 /arch/arm/cpu/armv7/am33xx
parent2c95211167091e543e20f4f457d3d1f1f660a6d4 (diff)
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am43xx: Tune the system to avoid DSS underflows
* This is done by limiting the ARM's bandwidth and setting DSS priority in the EMIF controller to ensure underflows do not occur.
Diffstat (limited to 'arch/arm/cpu/armv7/am33xx')
-rw-r--r--arch/arm/cpu/armv7/am33xx/ddr.c12
1 files changed, 12 insertions, 0 deletions
diff --git a/arch/arm/cpu/armv7/am33xx/ddr.c b/arch/arm/cpu/armv7/am33xx/ddr.c
index bbe9d1a..fc66872 100644
--- a/arch/arm/cpu/armv7/am33xx/ddr.c
+++ b/arch/arm/cpu/armv7/am33xx/ddr.c
@@ -94,6 +94,18 @@ void config_sdram_emif4d5(const struct emif_regs *regs, int nr)
writel(regs->emif_rd_wr_exec_thresh,
&emif_reg[nr]->emif_rd_wr_exec_thresh);
+ /*
+ * for most SOCs these registers won't need to be changed so only
+ * write to these registers if someone explicitly has set the
+ * register's value.
+ */
+ if(regs->emif_cos_config) {
+ writel(regs->emif_prio_class_serv_map, &emif_reg[nr]->emif_prio_class_serv_map);
+ writel(regs->emif_connect_id_serv_1_map, &emif_reg[nr]->emif_connect_id_serv_1_map);
+ writel(regs->emif_connect_id_serv_2_map, &emif_reg[nr]->emif_connect_id_serv_2_map);
+ writel(regs->emif_cos_config, &emif_reg[nr]->emif_cos_config);
+ }
+
writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl);
writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl_shdw);
writel(regs->sdram_config, &emif_reg[nr]->emif_sdram_config);