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| author | Tom Rini <trini@ti.com> | 2012-07-03 09:20:06 -0700 |
|---|---|---|
| committer | Albert ARIBAUD <albert.u.boot@aribaud.net> | 2012-09-01 14:58:12 +0200 |
| commit | b971dfad6a1c8c37857390d847ee22ec7af4aee2 (patch) | |
| tree | 5aa03e913128f11e30a96fc0878faa38234c2f38 /arch/arm/cpu/armv7/am33xx/clock.c | |
| parent | fda35eb982a6846c776bd94ba4b24bf43cbfe328 (diff) | |
| download | u-boot-imx-b971dfad6a1c8c37857390d847ee22ec7af4aee2.zip u-boot-imx-b971dfad6a1c8c37857390d847ee22ec7af4aee2.tar.gz u-boot-imx-b971dfad6a1c8c37857390d847ee22ec7af4aee2.tar.bz2 | |
am33xx: Move the call to ddr_pll_config, make it take the frequency
Depending on if we have DDR2 or DDR3 on the board we will need to call
ddr_pll_config with a different value. This call can be delayed
slightly to the point where we know which type of memory we have.
Signed-off-by: Tom Rini <trini@ti.com>
Diffstat (limited to 'arch/arm/cpu/armv7/am33xx/clock.c')
| -rw-r--r-- | arch/arm/cpu/armv7/am33xx/clock.c | 5 |
1 files changed, 2 insertions, 3 deletions
diff --git a/arch/arm/cpu/armv7/am33xx/clock.c b/arch/arm/cpu/armv7/am33xx/clock.c index f068824..1071f92 100644 --- a/arch/arm/cpu/armv7/am33xx/clock.c +++ b/arch/arm/cpu/armv7/am33xx/clock.c @@ -246,7 +246,7 @@ static void per_pll_config(void) ; } -static void ddr_pll_config(void) +void ddr_pll_config(unsigned int ddrpll_m) { u32 clkmode, clksel, div_m2; @@ -264,7 +264,7 @@ static void ddr_pll_config(void) ; clksel = clksel & (~CLK_SEL_MASK); - clksel = clksel | ((DDRPLL_M << CLK_SEL_SHIFT) | DDRPLL_N); + clksel = clksel | ((ddrpll_m << CLK_SEL_SHIFT) | DDRPLL_N); writel(clksel, &cmwkup->clkseldpllddr); div_m2 = div_m2 & CLK_DIV_SEL; @@ -298,7 +298,6 @@ void pll_init() mpu_pll_config(); core_pll_config(); per_pll_config(); - ddr_pll_config(); /* Enable the required interconnect clocks */ enable_interface_clocks(); |