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authorFabio Estevam <fabio.estevam@freescale.com>2013-05-03 04:37:11 +0000
committerStefano Babic <sbabic@denx.de>2013-05-05 17:08:46 +0200
commitb0d4bf9f0c061945e5b87150fc364e8794162a10 (patch)
treeceb20daff7109aa96bdf6876a0ac844a9df74dca /arch/arm/cpu/arm926ejs
parent8a47c997c57271222bf71e8c9f5a2fac4109a0bd (diff)
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mxs: spl_mem_init: Remove erroneous DDR setting
On mx23 there is no 'DRAM init complete' in register HW_DRAM_CTL18. Remove this erroneous setting. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Diffstat (limited to 'arch/arm/cpu/arm926ejs')
-rw-r--r--arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c4
1 files changed, 0 insertions, 4 deletions
diff --git a/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c b/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c
index 300da0a..df25535 100644
--- a/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c
+++ b/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c
@@ -279,10 +279,6 @@ static void mx23_mem_init(void)
setbits_le32(MXS_DRAM_BASE + 0x40, 1 << 19);
setbits_le32(MXS_DRAM_BASE + 0x40, 1 << 11);
-
- /* Wait for bit 10 (DRAM init complete) in DRAM_CTL18 */
- while (!(readl(MXS_DRAM_BASE + 0x48) & (1 << 10)))
- ;
}
#endif