Merge branch 'master' of git://git.denx.de/u-boot-arm

15 files changed, 74 insertions, 71 deletions

diff --git a/arch/arm/cpu/arm926ejs/armada100/timer.c b/arch/arm/cpu/arm926ejs/armada100/timer.c
index 355cd6d..948607f 100644
--- a/arch/arm/cpu/arm926ejs/armada100/timer.c
+++ b/arch/arm/cpu/arm926ejs/armada100/timer.c
@@ -61,7 +61,7 @@ struct armd1tmr_registers {
 #define	COUNT_RD_REQ		0x1
 
 DECLARE_GLOBAL_DATA_PTR;
-/* Using gd->tbu from timestamp and gd->tbl for lastdec */
+/* Using gd->arch.tbu from timestamp and gd->arch.tbl for lastdec */
 
 /* For preventing risk of instability in reading counter value,
  * first set read request to register cvwr and then read same
@@ -82,16 +82,16 @@ ulong get_timer_masked(void)
 {
 	ulong now = read_timer();
 
-	if (now >= gd->tbl) {
+	if (now >= gd->arch.tbl) {
 		/* normal mode */
-		gd->tbu += now - gd->tbl;
+		gd->arch.tbu += now - gd->arch.tbl;
 	} else {
 		/* we have an overflow ... */
-		gd->tbu += now + TIMER_LOAD_VAL - gd->tbl;
+		gd->arch.tbu += now + TIMER_LOAD_VAL - gd->arch.tbl;
 	}
-	gd->tbl = now;
+	gd->arch.tbl = now;
 
-	return gd->tbu;
+	return gd->arch.tbu;
 }
 
 ulong get_timer(ulong base)
@@ -135,9 +135,9 @@ int timer_init(void)
 
 	/* Enable timer 0 */
 	writel(0x1, &armd1timers->cer);
-	/* init the gd->tbu and gd->tbl value */
-	gd->tbl = read_timer();
-	gd->tbu = 0;
+	/* init the gd->arch.tbu and gd->arch.tbl value */
+	gd->arch.tbl = read_timer();
+	gd->arch.tbu = 0;
 
 	return 0;
 }
diff --git a/arch/arm/cpu/arm926ejs/at91/clock.c b/arch/arm/cpu/arm926ejs/at91/clock.c
index dc5c6c4..f825388 100644
--- a/arch/arm/cpu/arm926ejs/at91/clock.c
+++ b/arch/arm/cpu/arm926ejs/at91/clock.c
@@ -29,11 +29,11 @@ static unsigned long at91_css_to_rate(unsigned long css)
 	case AT91_PMC_MCKR_CSS_SLOW:
 		return CONFIG_SYS_AT91_SLOW_CLOCK;
 	case AT91_PMC_MCKR_CSS_MAIN:
-		return gd->main_clk_rate_hz;
+		return gd->arch.main_clk_rate_hz;
 	case AT91_PMC_MCKR_CSS_PLLA:
-		return gd->plla_rate_hz;
+		return gd->arch.plla_rate_hz;
 	case AT91_PMC_MCKR_CSS_PLLB:
-		return gd->pllb_rate_hz;
+		return gd->arch.pllb_rate_hz;
 	}
 
 	return 0;
@@ -132,10 +132,10 @@ int at91_clock_init(unsigned long main_clock)
 		main_clock = tmp * (CONFIG_SYS_AT91_SLOW_CLOCK / 16);
 	}
 #endif
-	gd->main_clk_rate_hz = main_clock;
+	gd->arch.main_clk_rate_hz = main_clock;
 
 	/* report if PLLA is more than mildly overclocked */
-	gd->plla_rate_hz = at91_pll_rate(main_clock, readl(&pmc->pllar));
+	gd->arch.plla_rate_hz = at91_pll_rate(main_clock, readl(&pmc->pllar));
 
 #ifdef CONFIG_USB_ATMEL
 	/*
@@ -144,9 +144,10 @@ int at91_clock_init(unsigned long main_clock)
 	 *
 	 * REVISIT:  assumes MCK doesn't derive from PLLB!
 	 */
-	gd->at91_pllb_usb_init = at91_pll_calc(main_clock, 48000000 * 2) |
+	gd->arch.at91_pllb_usb_init = at91_pll_calc(main_clock, 48000000 * 2) |
 			     AT91_PMC_PLLBR_USBDIV_2;
-	gd->pllb_rate_hz = at91_pll_rate(main_clock, gd->at91_pllb_usb_init);
+	gd->arch.pllb_rate_hz = at91_pll_rate(main_clock,
+					      gd->arch.at91_pllb_usb_init);
 #endif
 
 	/*
@@ -157,15 +158,15 @@ int at91_clock_init(unsigned long main_clock)
 #if defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9M10G45) \
 		|| defined(CONFIG_AT91SAM9X5)
 	/* plla divisor by 2 */
-	gd->plla_rate_hz /= (1 << ((mckr & 1 << 12) >> 12));
+	gd->arch.plla_rate_hz /= (1 << ((mckr & 1 << 12) >> 12));
 #endif
-	gd->mck_rate_hz = at91_css_to_rate(mckr & AT91_PMC_MCKR_CSS_MASK);
-	freq = gd->mck_rate_hz;
+	gd->arch.mck_rate_hz = at91_css_to_rate(mckr & AT91_PMC_MCKR_CSS_MASK);
+	freq = gd->arch.mck_rate_hz;
 
 	freq /= (1 << ((mckr & AT91_PMC_MCKR_PRES_MASK) >> 2));	/* prescale */
 #if defined(CONFIG_AT91SAM9G20)
 	/* mdiv ; (x >> 7) = ((x >> 8) * 2) */
-	gd->mck_rate_hz = (mckr & AT91_PMC_MCKR_MDIV_MASK) ?
+	gd->arch.mck_rate_hz = (mckr & AT91_PMC_MCKR_MDIV_MASK) ?
 		freq / ((mckr & AT91_PMC_MCKR_MDIV_MASK) >> 7) : freq;
 	if (mckr & AT91_PMC_MCKR_MDIV_MASK)
 		freq /= 2;			/* processor clock division */
@@ -177,14 +178,15 @@ int at91_clock_init(unsigned long main_clock)
 	 *  2   <==>   4
 	 *  3   <==>   3
 	 */
-	gd->mck_rate_hz = (mckr & AT91_PMC_MCKR_MDIV_MASK) ==
+	gd->arch.mck_rate_hz = (mckr & AT91_PMC_MCKR_MDIV_MASK) ==
 		(AT91_PMC_MCKR_MDIV_2 | AT91_PMC_MCKR_MDIV_4)
 		? freq / 3
 		: freq / (1 << ((mckr & AT91_PMC_MCKR_MDIV_MASK) >> 8));
 #else
-	gd->mck_rate_hz = freq / (1 << ((mckr & AT91_PMC_MCKR_MDIV_MASK) >> 8));
+	gd->arch.mck_rate_hz = freq /
+			(1 << ((mckr & AT91_PMC_MCKR_MDIV_MASK) >> 8));
 #endif
-	gd->cpu_clk_rate_hz = freq;
+	gd->arch.cpu_clk_rate_hz = freq;
 
 	return 0;
 }
diff --git a/arch/arm/cpu/arm926ejs/at91/timer.c b/arch/arm/cpu/arm926ejs/at91/timer.c
index f70ce83..4443fef 100644
--- a/arch/arm/cpu/arm926ejs/at91/timer.c
+++ b/arch/arm/cpu/arm926ejs/at91/timer.c
@@ -52,14 +52,14 @@ DECLARE_GLOBAL_DATA_PTR;
 static inline unsigned long long tick_to_time(unsigned long long tick)
 {
 	tick *= CONFIG_SYS_HZ;
-	do_div(tick, gd->timer_rate_hz);
+	do_div(tick, gd->arch.timer_rate_hz);
 
 	return tick;
 }
 
 static inline unsigned long long usec_to_tick(unsigned long long usec)
 {
-	usec *= gd->timer_rate_hz;
+	usec *= gd->arch.timer_rate_hz;
 	do_div(usec, 1000000);
 
 	return usec;
@@ -79,8 +79,8 @@ int timer_init(void)
 	/* Enable PITC */
 	writel(TIMER_LOAD_VAL | AT91_PIT_MR_EN , &pit->mr);
 
-	gd->timer_rate_hz = gd->mck_rate_hz / 16;
-	gd->tbu = gd->tbl = 0;
+	gd->arch.timer_rate_hz = gd->arch.mck_rate_hz / 16;
+	gd->arch.tbu = gd->arch.tbl = 0;
 
 	return 0;
 }
@@ -95,10 +95,10 @@ unsigned long long get_ticks(void)
 	ulong now = readl(&pit->piir);
 
 	/* increment tbu if tbl has rolled over */
-	if (now < gd->tbl)
-		gd->tbu++;
-	gd->tbl = now;
-	return (((unsigned long long)gd->tbu) << 32) | gd->tbl;
+	if (now < gd->arch.tbl)
+		gd->arch.tbu++;
+	gd->arch.tbl = now;
+	return (((unsigned long long)gd->arch.tbu) << 32) | gd->arch.tbl;
 }
 
 void __udelay(unsigned long usec)
@@ -132,5 +132,5 @@ ulong get_timer(ulong base)
  */
 ulong get_tbclk(void)
 {
-	return gd->timer_rate_hz;
+	return gd->arch.timer_rate_hz;
 }
diff --git a/arch/arm/cpu/arm926ejs/davinci/timer.c b/arch/arm/cpu/arm926ejs/davinci/timer.c
index 93c9e60..4142932 100644
--- a/arch/arm/cpu/arm926ejs/davinci/timer.c
+++ b/arch/arm/cpu/arm926ejs/davinci/timer.c
@@ -60,8 +60,8 @@ int timer_init(void)
 	writel(0x0, &timer->tim34);
 	writel(TIMER_LOAD_VAL, &timer->prd34);
 	writel(2 << 22, &timer->tcr);
-	gd->timer_rate_hz = CONFIG_SYS_HZ_CLOCK / TIM_CLK_DIV;
-	gd->timer_reset_value = 0;
+	gd->arch.timer_rate_hz = CONFIG_SYS_HZ_CLOCK / TIM_CLK_DIV;
+	gd->arch.timer_reset_value = 0;
 
 	return(0);
 }
@@ -74,27 +74,28 @@ unsigned long long get_ticks(void)
 	unsigned long now = readl(&timer->tim34);
 
 	/* increment tbu if tbl has rolled over */
-	if (now < gd->tbl)
-		gd->tbu++;
-	gd->tbl = now;
+	if (now < gd->arch.tbl)
+		gd->arch.tbu++;
+	gd->arch.tbl = now;
 
-	return (((unsigned long long)gd->tbu) << 32) | gd->tbl;
+	return (((unsigned long long)gd->arch.tbu) << 32) | gd->arch.tbl;
 }
 
 ulong get_timer(ulong base)
 {
 	unsigned long long timer_diff;
 
-	timer_diff = get_ticks() - gd->timer_reset_value;
+	timer_diff = get_ticks() - gd->arch.timer_reset_value;
 
-	return lldiv(timer_diff, (gd->timer_rate_hz / CONFIG_SYS_HZ)) - base;
+	return lldiv(timer_diff,
+		     (gd->arch.timer_rate_hz / CONFIG_SYS_HZ)) - base;
 }
 
 void __udelay(unsigned long usec)
 {
 	unsigned long long endtime;
 
-	endtime = lldiv((unsigned long long)usec * gd->timer_rate_hz,
+	endtime = lldiv((unsigned long long)usec * gd->arch.timer_rate_hz,
 			1000000UL);
 	endtime += get_ticks();
 
@@ -108,7 +109,7 @@ void __udelay(unsigned long usec)
  */
 ulong get_tbclk(void)
 {
-	return gd->timer_rate_hz;
+	return gd->arch.timer_rate_hz;
 }
 
 #ifdef CONFIG_HW_WATCHDOG
diff --git a/arch/arm/cpu/arm926ejs/kirkwood/timer.c b/arch/arm/cpu/arm926ejs/kirkwood/timer.c
index f5d0160..85e81e3 100644
--- a/arch/arm/cpu/arm926ejs/kirkwood/timer.c
+++ b/arch/arm/cpu/arm926ejs/kirkwood/timer.c
@@ -86,8 +86,8 @@ struct kwtmr_registers *kwtmr_regs = (struct kwtmr_registers *)KW_TIMER_BASE;
 
 DECLARE_GLOBAL_DATA_PTR;
 
-#define timestamp gd->tbl
-#define lastdec gd->lastinc
+#define timestamp gd->arch.tbl
+#define lastdec gd->arch.lastinc
 
 ulong get_timer_masked(void)
 {
diff --git a/arch/arm/cpu/arm926ejs/mb86r0x/timer.c b/arch/arm/cpu/arm926ejs/mb86r0x/timer.c
index 75314b9..c6486c1 100644
--- a/arch/arm/cpu/arm926ejs/mb86r0x/timer.c
+++ b/arch/arm/cpu/arm926ejs/mb86r0x/timer.c
@@ -35,8 +35,8 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-#define timestamp gd->tbl
-#define lastdec gd->lastinc
+#define timestamp gd->arch.tbl
+#define lastdec gd->arch.lastinc
 
 static inline unsigned long long tick_to_time(unsigned long long tick)
 {
diff --git a/arch/arm/cpu/arm926ejs/mx25/generic.c b/arch/arm/cpu/arm926ejs/mx25/generic.c
index b991418..679273b 100644
--- a/arch/arm/cpu/arm926ejs/mx25/generic.c
+++ b/arch/arm/cpu/arm926ejs/mx25/generic.c
@@ -229,9 +229,9 @@ int get_clocks(void)
 {
 #ifdef CONFIG_FSL_ESDHC
 #if CONFIG_SYS_FSL_ESDHC_ADDR == IMX_MMC_SDHC2_BASE
-	gd->sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
+	gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
 #else
-	gd->sdhc_clk = mxc_get_clock(MXC_ESDHC1_CLK);
+	gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC1_CLK);
 #endif
 #endif
 	return 0;
diff --git a/arch/arm/cpu/arm926ejs/mx25/timer.c b/arch/arm/cpu/arm926ejs/mx25/timer.c
index 4dc4041..f8bebcc 100644
--- a/arch/arm/cpu/arm926ejs/mx25/timer.c
+++ b/arch/arm/cpu/arm926ejs/mx25/timer.c
@@ -44,8 +44,8 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-#define timestamp	(gd->tbl)
-#define lastinc		(gd->lastinc)
+#define timestamp	(gd->arch.tbl)
+#define lastinc		(gd->arch.lastinc)
 
 /*
  * "time" is measured in 1 / CONFIG_SYS_HZ seconds,
diff --git a/arch/arm/cpu/arm926ejs/mx27/timer.c b/arch/arm/cpu/arm926ejs/mx27/timer.c
index a5dd684..07e132a 100644
--- a/arch/arm/cpu/arm926ejs/mx27/timer.c
+++ b/arch/arm/cpu/arm926ejs/mx27/timer.c
@@ -45,8 +45,8 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-#define timestamp	(gd->tbl)
-#define lastinc		(gd->lastinc)
+#define timestamp	(gd->arch.tbl)
+#define lastinc		(gd->arch.lastinc)
 
 /*
  * "time" is measured in 1 / CONFIG_SYS_HZ seconds,
diff --git a/arch/arm/cpu/arm926ejs/mxs/timer.c b/arch/arm/cpu/arm926ejs/mxs/timer.c
index 4ed75e6..3738411 100644
--- a/arch/arm/cpu/arm926ejs/mxs/timer.c
+++ b/arch/arm/cpu/arm926ejs/mxs/timer.c
@@ -36,8 +36,8 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-#define timestamp (gd->tbl)
-#define lastdec (gd->lastinc)
+#define timestamp (gd->arch.tbl)
+#define lastdec (gd->arch.lastinc)
 
 /*
  * This driver uses 1kHz clock source.
diff --git a/arch/arm/cpu/arm926ejs/omap/timer.c b/arch/arm/cpu/arm926ejs/omap/timer.c
index 390c9c8..34ec7b2 100644
--- a/arch/arm/cpu/arm926ejs/omap/timer.c
+++ b/arch/arm/cpu/arm926ejs/omap/timer.c
@@ -44,8 +44,8 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-#define timestamp gd->tbl
-#define lastdec gd->lastinc
+#define timestamp gd->arch.tbl
+#define lastdec gd->arch.lastinc
 
 int timer_init (void)
 {
diff --git a/arch/arm/cpu/arm926ejs/orion5x/timer.c b/arch/arm/cpu/arm926ejs/orion5x/timer.c
index 8a8aaf1..f723351 100644
--- a/arch/arm/cpu/arm926ejs/orion5x/timer.c
+++ b/arch/arm/cpu/arm926ejs/orion5x/timer.c
@@ -92,8 +92,8 @@ static inline ulong read_timer(void)
 
 DECLARE_GLOBAL_DATA_PTR;
 
-#define timestamp gd->tbl
-#define lastdec gd->lastinc
+#define timestamp gd->arch.tbl
+#define lastdec gd->arch.lastinc
 
 ulong get_timer_masked(void)
 {
diff --git a/arch/arm/cpu/arm926ejs/pantheon/timer.c b/arch/arm/cpu/arm926ejs/pantheon/timer.c
index 28aadad..2d9ddba 100644
--- a/arch/arm/cpu/arm926ejs/pantheon/timer.c
+++ b/arch/arm/cpu/arm926ejs/pantheon/timer.c
@@ -60,7 +60,7 @@ struct panthtmr_registers {
 #define	COUNT_RD_REQ		0x1
 
 DECLARE_GLOBAL_DATA_PTR;
-/* Using gd->tbu from timestamp and gd->tbl for lastdec */
+/* Using gd->arch.tbu from timestamp and gd->arch.tbl for lastdec */
 
 /*
  * For preventing risk of instability in reading counter value,
@@ -90,16 +90,16 @@ ulong get_timer_masked(void)
 {
 	ulong now = read_timer();
 
-	if (now >= gd->tbl) {
+	if (now >= gd->arch.tbl) {
 		/* normal mode */
-		gd->tbu += now - gd->tbl;
+		gd->arch.tbu += now - gd->arch.tbl;
 	} else {
 		/* we have an overflow ... */
-		gd->tbu += now + TIMER_LOAD_VAL - gd->tbl;
+		gd->arch.tbu += now + TIMER_LOAD_VAL - gd->arch.tbl;
 	}
-	gd->tbl = now;
+	gd->arch.tbl = now;
 
-	return gd->tbu;
+	return gd->arch.tbu;
 }
 
 ulong get_timer(ulong base)
@@ -144,9 +144,9 @@ int timer_init(void)
 
 	/* Enable timer 0 */
 	writel(0x1, &panthtimers->cer);
-	/* init the gd->tbu and gd->tbl value */
-	gd->tbl = read_timer();
-	gd->tbu = 0;
+	/* init the gd->arch.tbu and gd->arch.tbl value */
+	gd->arch.tbl = read_timer();
+	gd->arch.tbu = 0;
 
 	return 0;
 }
diff --git a/arch/arm/cpu/arm926ejs/spear/timer.c b/arch/arm/cpu/arm926ejs/spear/timer.c
index 1dc7860..de4ba7b 100644
--- a/arch/arm/cpu/arm926ejs/spear/timer.c
+++ b/arch/arm/cpu/arm926ejs/spear/timer.c
@@ -38,8 +38,8 @@ static struct misc_regs *const misc_regs_p =
 
 DECLARE_GLOBAL_DATA_PTR;
 
-#define timestamp gd->tbl
-#define lastdec gd->lastinc
+#define timestamp gd->arch.tbl
+#define lastdec gd->arch.lastinc
 
 int timer_init(void)
 {
diff --git a/arch/arm/cpu/arm926ejs/versatile/timer.c b/arch/arm/cpu/arm926ejs/versatile/timer.c
index f58e151..b36d6d9 100644
--- a/arch/arm/cpu/arm926ejs/versatile/timer.c
+++ b/arch/arm/cpu/arm926ejs/versatile/timer.c
@@ -44,8 +44,8 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-#define timestamp gd->tbl
-#define lastdec gd->lastinc
+#define timestamp gd->arch.tbl
+#define lastdec gd->arch.lastinc
 
 #define TIMER_ENABLE	(1 << 7)
 #define TIMER_MODE_MSK	(1 << 6)