diff options
author | Albert ARIBAUD <albert.u.boot@aribaud.net> | 2013-03-15 15:18:31 +0100 |
---|---|---|
committer | Albert ARIBAUD <albert.u.boot@aribaud.net> | 2013-03-15 15:18:31 +0100 |
commit | 6579d15c58e2b6b051f126ea8b77dd767252aa14 (patch) | |
tree | cac9f9205db8c28a764ad8282d3a909bf95e8db4 /arch/arm/cpu/arm926ejs | |
parent | c44bb3a30f5a1332176edce1a91c0e2cf666ee8f (diff) | |
parent | 19a0f7fa271de0345bb2df90d443c547c41e8037 (diff) | |
download | u-boot-imx-6579d15c58e2b6b051f126ea8b77dd767252aa14.zip u-boot-imx-6579d15c58e2b6b051f126ea8b77dd767252aa14.tar.gz u-boot-imx-6579d15c58e2b6b051f126ea8b77dd767252aa14.tar.bz2 |
Merge branch 'u-boot-imx/master' into 'u-boot-arm/master'
Diffstat (limited to 'arch/arm/cpu/arm926ejs')
-rw-r--r-- | arch/arm/cpu/arm926ejs/config.mk | 2 | ||||
-rw-r--r-- | arch/arm/cpu/arm926ejs/mxs/clock.c | 3 | ||||
-rw-r--r-- | arch/arm/cpu/arm926ejs/mxs/mxs_init.h | 2 | ||||
-rw-r--r-- | arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c | 16 | ||||
-rw-r--r-- | arch/arm/cpu/arm926ejs/mxs/spl_power_init.c | 2 | ||||
-rw-r--r-- | arch/arm/cpu/arm926ejs/mxs/timer.c | 39 |
6 files changed, 48 insertions, 16 deletions
diff --git a/arch/arm/cpu/arm926ejs/config.mk b/arch/arm/cpu/arm926ejs/config.mk index 47f24f5..6a3a1bb 100644 --- a/arch/arm/cpu/arm926ejs/config.mk +++ b/arch/arm/cpu/arm926ejs/config.mk @@ -34,6 +34,6 @@ PLATFORM_RELFLAGS += $(PF_RELFLAGS_SLB_AT) ifneq ($(CONFIG_IMX_CONFIG),) -ALL-y += $(OBJTREE)/u-boot.imx +ALL-y += $(obj)u-boot.imx endif diff --git a/arch/arm/cpu/arm926ejs/mxs/clock.c b/arch/arm/cpu/arm926ejs/mxs/clock.c index 00b9aba..43e7663 100644 --- a/arch/arm/cpu/arm926ejs/mxs/clock.c +++ b/arch/arm/cpu/arm926ejs/mxs/clock.c @@ -289,7 +289,8 @@ static uint32_t mxs_get_sspclk(enum mxs_sspclock ssp) void mxs_set_ssp_busclock(unsigned int bus, uint32_t freq) { struct mxs_ssp_regs *ssp_regs; - const uint32_t sspclk = mxs_get_sspclk(bus); + const enum mxs_sspclock clk = mxs_ssp_clock_by_bus(bus); + const uint32_t sspclk = mxs_get_sspclk(clk); uint32_t reg; uint32_t divide, rate, tgtclk; diff --git a/arch/arm/cpu/arm926ejs/mxs/mxs_init.h b/arch/arm/cpu/arm926ejs/mxs/mxs_init.h index 2ddc5bc..084def5 100644 --- a/arch/arm/cpu/arm926ejs/mxs/mxs_init.h +++ b/arch/arm/cpu/arm926ejs/mxs/mxs_init.h @@ -30,7 +30,7 @@ void early_delay(int delay); void mxs_power_init(void); -#ifdef CONFIG_SPL_MX28_PSWITCH_WAIT +#ifdef CONFIG_SPL_MXS_PSWITCH_WAIT void mxs_power_wait_pswitch(void); #else static inline void mxs_power_wait_pswitch(void) { } diff --git a/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c b/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c index f8392f6..fdac73c 100644 --- a/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c +++ b/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c @@ -27,6 +27,7 @@ #include <config.h> #include <asm/io.h> #include <asm/arch/imx-regs.h> +#include <asm/arch/sys_proto.h> #include <linux/compiler.h> #include "mxs_init.h" @@ -119,6 +120,10 @@ static void initialize_dram_values(void) writel(dram_vals[i], MXS_DRAM_BASE + (4 * i)); #ifdef CONFIG_MX23 + /* + * Enable tRAS lockout in HW_DRAM_CTL08 ; it must be the last + * element to be set + */ writel((1 << 24), MXS_DRAM_BASE + (4 * 8)); #endif } @@ -229,7 +234,7 @@ static void mx23_mem_setup_vddmem(void) struct mxs_power_regs *power_regs = (struct mxs_power_regs *)MXS_POWER_BASE; - writel((0x12 << POWER_VDDMEMCTRL_TRG_OFFSET) | + writel((0x10 << POWER_VDDMEMCTRL_TRG_OFFSET) | POWER_VDDMEMCTRL_ENABLE_ILIMIT | POWER_VDDMEMCTRL_ENABLE_LINREG | POWER_VDDMEMCTRL_PULLDOWN_ACTIVE, @@ -237,13 +242,20 @@ static void mx23_mem_setup_vddmem(void) early_delay(10000); - writel((0x12 << POWER_VDDMEMCTRL_TRG_OFFSET) | + writel((0x10 << POWER_VDDMEMCTRL_TRG_OFFSET) | POWER_VDDMEMCTRL_ENABLE_LINREG, &power_regs->hw_power_vddmemctrl); } static void mx23_mem_init(void) { + /* + * Reset/ungate the EMI block. This is essential, otherwise the system + * suffers from memory instability. This thing is mx23 specific and is + * no longer present on mx28. + */ + mxs_reset_block((struct mxs_register_32 *)MXS_EMI_BASE); + mx23_mem_setup_vddmem(); /* diff --git a/arch/arm/cpu/arm926ejs/mxs/spl_power_init.c b/arch/arm/cpu/arm926ejs/mxs/spl_power_init.c index e9d6302..287c698 100644 --- a/arch/arm/cpu/arm926ejs/mxs/spl_power_init.c +++ b/arch/arm/cpu/arm926ejs/mxs/spl_power_init.c @@ -921,7 +921,7 @@ void mxs_power_init(void) early_delay(1000); } -#ifdef CONFIG_SPL_MX28_PSWITCH_WAIT +#ifdef CONFIG_SPL_MXS_PSWITCH_WAIT void mxs_power_wait_pswitch(void) { struct mxs_power_regs *power_regs = diff --git a/arch/arm/cpu/arm926ejs/mxs/timer.c b/arch/arm/cpu/arm926ejs/mxs/timer.c index 3738411..2039106 100644 --- a/arch/arm/cpu/arm926ejs/mxs/timer.c +++ b/arch/arm/cpu/arm926ejs/mxs/timer.c @@ -32,7 +32,11 @@ #include <asm/arch/sys_proto.h> /* Maximum fixed count */ -#define TIMER_LOAD_VAL 0xffffffff +#if defined(CONFIG_MX23) +#define TIMER_LOAD_VAL 0xffff +#elif defined(CONFIG_MX28) +#define TIMER_LOAD_VAL 0xffffffff +#endif DECLARE_GLOBAL_DATA_PTR; @@ -42,22 +46,22 @@ DECLARE_GLOBAL_DATA_PTR; /* * This driver uses 1kHz clock source. */ -#define MX28_INCREMENTER_HZ 1000 +#define MXS_INCREMENTER_HZ 1000 static inline unsigned long tick_to_time(unsigned long tick) { - return tick / (MX28_INCREMENTER_HZ / CONFIG_SYS_HZ); + return tick / (MXS_INCREMENTER_HZ / CONFIG_SYS_HZ); } static inline unsigned long time_to_tick(unsigned long time) { - return time * (MX28_INCREMENTER_HZ / CONFIG_SYS_HZ); + return time * (MXS_INCREMENTER_HZ / CONFIG_SYS_HZ); } /* Calculate how many ticks happen in "us" microseconds */ static inline unsigned long us_to_tick(unsigned long us) { - return (us * MX28_INCREMENTER_HZ) / 1000000; + return (us * MXS_INCREMENTER_HZ) / 1000000; } int timer_init(void) @@ -69,7 +73,11 @@ int timer_init(void) mxs_reset_block(&timrot_regs->hw_timrot_rotctrl_reg); /* Set fixed_count to 0 */ +#if defined(CONFIG_MX23) + writel(0, &timrot_regs->hw_timrot_timcount0); +#elif defined(CONFIG_MX28) writel(0, &timrot_regs->hw_timrot_fixed_count0); +#endif /* Set UPDATE bit and 1Khz frequency */ writel(TIMROT_TIMCTRLn_UPDATE | TIMROT_TIMCTRLn_RELOAD | @@ -77,7 +85,11 @@ int timer_init(void) &timrot_regs->hw_timrot_timctrl0); /* Set fixed_count to maximal value */ +#if defined(CONFIG_MX23) + writel(TIMER_LOAD_VAL - 1, &timrot_regs->hw_timrot_timcount0); +#elif defined(CONFIG_MX28) writel(TIMER_LOAD_VAL, &timrot_regs->hw_timrot_fixed_count0); +#endif return 0; } @@ -86,9 +98,16 @@ unsigned long long get_ticks(void) { struct mxs_timrot_regs *timrot_regs = (struct mxs_timrot_regs *)MXS_TIMROT_BASE; + uint32_t now; /* Current tick value */ - uint32_t now = readl(&timrot_regs->hw_timrot_running_count0); +#if defined(CONFIG_MX23) + /* Upper bits are the valid ones. */ + now = readl(&timrot_regs->hw_timrot_timcount0) >> + TIMROT_RUNNING_COUNTn_RUNNING_COUNT_OFFSET; +#elif defined(CONFIG_MX28) + now = readl(&timrot_regs->hw_timrot_running_count0); +#endif if (lastdec >= now) { /* @@ -117,17 +136,17 @@ ulong get_timer(ulong base) } /* We use the HW_DIGCTL_MICROSECONDS register for sub-millisecond timer. */ -#define MX28_HW_DIGCTL_MICROSECONDS 0x8001c0c0 +#define MXS_HW_DIGCTL_MICROSECONDS 0x8001c0c0 void __udelay(unsigned long usec) { uint32_t old, new, incr; uint32_t counter = 0; - old = readl(MX28_HW_DIGCTL_MICROSECONDS); + old = readl(MXS_HW_DIGCTL_MICROSECONDS); while (counter < usec) { - new = readl(MX28_HW_DIGCTL_MICROSECONDS); + new = readl(MXS_HW_DIGCTL_MICROSECONDS); /* Check if the timer wrapped. */ if (new < old) { @@ -152,5 +171,5 @@ void __udelay(unsigned long usec) ulong get_tbclk(void) { - return MX28_INCREMENTER_HZ; + return MXS_INCREMENTER_HZ; } |