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author | Tom Rini <trini@ti.com> | 2013-10-02 11:45:22 -0400 |
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committer | Tom Rini <trini@ti.com> | 2013-10-02 11:45:22 -0400 |
commit | 6297872cd5de4705b6318778261b1f3f64a34c11 (patch) | |
tree | 7159ac1b03daa6906c8609b2515e42214f3bc422 /arch/arm/cpu/arm926ejs/mxs/start.S | |
parent | 0ae39166b1babbc86da4269458da9bce198bce55 (diff) | |
parent | f04c53762962280365005c9db12ab561a18f2692 (diff) | |
download | u-boot-imx-6297872cd5de4705b6318778261b1f3f64a34c11.zip u-boot-imx-6297872cd5de4705b6318778261b1f3f64a34c11.tar.gz u-boot-imx-6297872cd5de4705b6318778261b1f3f64a34c11.tar.bz2 |
Merge branch 'master' of git://git.denx.de/u-boot-arm
Diffstat (limited to 'arch/arm/cpu/arm926ejs/mxs/start.S')
-rw-r--r-- | arch/arm/cpu/arm926ejs/mxs/start.S | 50 |
1 files changed, 30 insertions, 20 deletions
diff --git a/arch/arm/cpu/arm926ejs/mxs/start.S b/arch/arm/cpu/arm926ejs/mxs/start.S index 94b2b3f..3e454ae 100644 --- a/arch/arm/cpu/arm926ejs/mxs/start.S +++ b/arch/arm/cpu/arm926ejs/mxs/start.S @@ -152,39 +152,49 @@ _reset: /* * Store all registers on old stack pointer, this will allow us later to * return to the BootROM and let the BootROM load U-Boot into RAM. + * + * WARNING: Register r0 and r1 are used by the BootROM to pass data + * to the called code. Register r0 will contain arbitrary + * data that are set in the BootStream. In case this code + * was started with CALL instruction, register r1 will contain + * pointer to the return value this function can then set. + * The code below MUST NOT CHANGE register r0 and r1 ! */ push {r0-r12,r14} - /* save control register c1 */ - mrc p15, 0, r0, c1, c0, 0 - push {r0} + /* Save control register c1 */ + mrc p15, 0, r2, c1, c0, 0 + push {r2} - /* - * set the cpu to SVC32 mode and store old CPSR register content - */ - mrs r0,cpsr - push {r0} - bic r0,r0,#0x1f - orr r0,r0,#0xd3 - msr cpsr,r0 + /* Set the cpu to SVC32 mode and store old CPSR register content. */ + mrs r2, cpsr + push {r2} + bic r2, r2, #0x1f + orr r2, r2, #0xd3 + msr cpsr, r2 bl board_init_ll + /* Restore BootROM's CPU mode (especially FIQ). */ + pop {r2} + msr cpsr,r2 + /* - * restore bootrom's cpu mode (especially FIQ) + * Restore c1 register. Especially set exception vector location + * back to BootROM space which is required by bootrom for USB boot. */ - pop {r0} - msr cpsr,r0 + pop {r2} + mcr p15, 0, r2, c1, c0, 0 + + pop {r0-r12,r14} /* - * restore c1 register - * (especially set exception vector location back to - * bootrom space which is required by bootrom for USB boot) + * In case this code was started by the CALL instruction, the register + * r0 is examined by the BootROM after this code returns. The value in + * r0 must be set to 0 to indicate successful return. */ - pop {r0} - mcr p15, 0, r0, c1, c0, 0 + mov r0, #0 - pop {r0-r12,r14} bx lr _hang: |