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author | Albert ARIBAUD \(3ADEV\) <albert.aribaud@3adev.fr> | 2015-03-31 11:40:51 +0200 |
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committer | Albert ARIBAUD <albert.u.boot@aribaud.net> | 2015-04-10 14:23:39 +0200 |
commit | 412ae53aadb53cd63e754d638bafe6e426aeafee (patch) | |
tree | 0bbf46fef21d002cc1a37b8f478e4b7a26c200d4 /arch/arm/cpu/arm926ejs/lpc32xx/lowlevel_init.S | |
parent | 8c80eb3b533c73a4b4a505fbaf925cdaafe0b5d2 (diff) | |
download | u-boot-imx-412ae53aadb53cd63e754d638bafe6e426aeafee.zip u-boot-imx-412ae53aadb53cd63e754d638bafe6e426aeafee.tar.gz u-boot-imx-412ae53aadb53cd63e754d638bafe6e426aeafee.tar.bz2 |
lpc32xx: add support for board work_92105
Work_92105 from Work Microwave is an LPC3250-
based board with the following features:
- 64MB or 128MB SDR DRAM
- 1 GB SLC NAND, managed through MLC controller.
- Ethernet
- Ethernet + PHY SMSC8710
- I2C:
- EEPROM (24M01-compatible)
- RTC (DS1374-compatible)
- Temperature sensor (DS620)
- DACs (2 x MAX518)
- SPI (through SSP interface)
- Port expander MAX6957
- LCD display (HD44780-compatible), controlled
through the port expander and DACs
This board has SPL support, and uses the LPC32XX boot
image format.
Signed-off-by: Albert ARIBAUD (3ADEV) <albert.aribaud@3adev.fr>
Diffstat (limited to 'arch/arm/cpu/arm926ejs/lpc32xx/lowlevel_init.S')
-rw-r--r-- | arch/arm/cpu/arm926ejs/lpc32xx/lowlevel_init.S | 45 |
1 files changed, 45 insertions, 0 deletions
diff --git a/arch/arm/cpu/arm926ejs/lpc32xx/lowlevel_init.S b/arch/arm/cpu/arm926ejs/lpc32xx/lowlevel_init.S new file mode 100644 index 0000000..4b8053e --- /dev/null +++ b/arch/arm/cpu/arm926ejs/lpc32xx/lowlevel_init.S @@ -0,0 +1,45 @@ +/* + * WORK Microwave work_92105 board low level init + * + * (C) Copyright 2014 DENX Software Engineering GmbH + * Written-by: Albert ARIBAUD <albert.aribaud@3adev.fr> + * + * Low level init is called from SPL to set up the clocks. + * On entry, the LPC3250 is in Direct Run mode with all clocks + * running at 13 MHz; on exit, ARM clock is 208 MHz, HCLK is + * 104 MHz and PCLK is 13 MHz. + * + * This code must run from SRAM so that the clock changes do + * not prevent it from executing. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +.globl lowlevel_init + +lowlevel_init: + + /* Set ARM, HCLK, PCLK dividers for normal mode */ + ldr r0, =0x0000003D + ldr r1, =0x40004040 + str r0, [r1] + + /* Start HCLK PLL for 208 MHz */ + ldr r0, =0x0001401E + ldr r1, =0x40004058 + str r0, [r1] + + /* wait for HCLK PLL to lock */ +1: + ldr r0, [r1] + ands r0, r0, #1 + beq 1b + + /* switch to normal mode */ + ldr r1, =0x40004044 + ldr r0, [r1] + orr r0, #0x00000004 + str r0, [r1] + + /* Return to U-boot via saved link register */ + mov pc, lr |