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authorLaurence Withers <lwithers@guralp.com>2012-07-30 23:30:36 +0000
committerAlbert ARIBAUD <albert.u.boot@aribaud.net>2012-09-01 14:58:14 +0200
commitde9d2e3d60dba1ab775ad67032b5afa00086f53f (patch)
tree666f1b6c167037c9873643cf262e20709ecbad87 /arch/arm/cpu/arm926ejs/davinci
parent88ac6b9d1402b5a7b639131df95bdd2dbd54d69d (diff)
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DaVinci DA8xx: replace magic number for DDR speed
Replace a magic number for the DDR2/mDDR PHY clock ID with a proper definition. In addition, don't request this clock ID on DA830 hardware, which does not have a DDR2/mDDR PHY (or associated PLL controller). Signed-off-by: Laurence Withers <lwithers@guralp.com> Cc: Tom Rini <trini@ti.com> Cc: Prabhakar Lad <prabhakar.csengg@gmail.com>
Diffstat (limited to 'arch/arm/cpu/arm926ejs/davinci')
-rw-r--r--arch/arm/cpu/arm926ejs/davinci/cpu.c3
1 files changed, 2 insertions, 1 deletions
diff --git a/arch/arm/cpu/arm926ejs/davinci/cpu.c b/arch/arm/cpu/arm926ejs/davinci/cpu.c
index 6cb857a..41201d0 100644
--- a/arch/arm/cpu/arm926ejs/davinci/cpu.c
+++ b/arch/arm/cpu/arm926ejs/davinci/cpu.c
@@ -194,7 +194,8 @@ int set_cpu_clk_info(void)
#ifdef CONFIG_SOC_DA8XX
gd->bd->bi_arm_freq = clk_get(DAVINCI_ARM_CLKID) / 1000000;
/* DDR PHY uses an x2 input clock */
- gd->bd->bi_ddr_freq = clk_get(0x10001) / 1000000;
+ gd->bd->bi_ddr_freq = cpu_is_da830() ? 0 :
+ (clk_get(DAVINCI_DDR_CLKID) / 1000000);
#else
unsigned int pllbase = DAVINCI_PLL_CNTRL0_BASE;