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| author | Jesse Gilles <jgilles@multitech.com> | 2013-02-27 23:42:49 +0000 |
|---|---|---|
| committer | Andreas Bießmann <andreas.devel@googlemail.com> | 2013-03-12 13:02:20 +0100 |
| commit | 08f0533a147ca37546a6539b43fce3916e82811a (patch) | |
| tree | 215a43ff51f9c11c9814527c799087a2d4ad2c70 /arch/arm/cpu/arm926ejs/at91 | |
| parent | fc14fbace4b295ffb22aa90d2791365f1dd6bb15 (diff) | |
| download | u-boot-imx-08f0533a147ca37546a6539b43fce3916e82811a.zip u-boot-imx-08f0533a147ca37546a6539b43fce3916e82811a.tar.gz u-boot-imx-08f0533a147ca37546a6539b43fce3916e82811a.tar.bz2 | |
ARM: sam9x5: fix ethernet pins in MII mode
Fix pin setting in MII mode
Signed-off-by: Jesse Gilles <jgilles@multitech.com>
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
Diffstat (limited to 'arch/arm/cpu/arm926ejs/at91')
| -rw-r--r-- | arch/arm/cpu/arm926ejs/at91/at91sam9x5_devices.c | 16 |
1 files changed, 8 insertions, 8 deletions
diff --git a/arch/arm/cpu/arm926ejs/at91/at91sam9x5_devices.c b/arch/arm/cpu/arm926ejs/at91/at91sam9x5_devices.c index 29e8aa4..9218546 100644 --- a/arch/arm/cpu/arm926ejs/at91/at91sam9x5_devices.c +++ b/arch/arm/cpu/arm926ejs/at91/at91sam9x5_devices.c @@ -246,14 +246,14 @@ void at91_macb_hw_init(void) #ifndef CONFIG_RMII /* Only emac0 support MII */ if (has_emac0()) { - at91_set_b_periph(AT91_PIO_PORTB, 16, 0); /* ECRS */ - at91_set_b_periph(AT91_PIO_PORTB, 17, 0); /* ECOL */ - at91_set_b_periph(AT91_PIO_PORTB, 13, 0); /* ERX2 */ - at91_set_b_periph(AT91_PIO_PORTB, 14, 0); /* ERX3 */ - at91_set_b_periph(AT91_PIO_PORTB, 15, 0); /* ERXCK */ - at91_set_b_periph(AT91_PIO_PORTB, 11, 0); /* ETX2 */ - at91_set_b_periph(AT91_PIO_PORTB, 12, 0); /* ETX3 */ - at91_set_b_periph(AT91_PIO_PORTB, 8, 0); /* ETXER */ + at91_set_a_periph(AT91_PIO_PORTB, 16, 0); /* ECRS */ + at91_set_a_periph(AT91_PIO_PORTB, 17, 0); /* ECOL */ + at91_set_a_periph(AT91_PIO_PORTB, 13, 0); /* ERX2 */ + at91_set_a_periph(AT91_PIO_PORTB, 14, 0); /* ERX3 */ + at91_set_a_periph(AT91_PIO_PORTB, 15, 0); /* ERXCK */ + at91_set_a_periph(AT91_PIO_PORTB, 11, 0); /* ETX2 */ + at91_set_a_periph(AT91_PIO_PORTB, 12, 0); /* ETX3 */ + at91_set_a_periph(AT91_PIO_PORTB, 8, 0); /* ETXER */ } #endif } |