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author | Stephen Warren <swarren@nvidia.com> | 2014-01-24 10:23:02 -0700 |
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committer | Tom Warren <twarren@nvidia.com> | 2014-02-03 09:46:45 -0700 |
commit | 9399e540ca5b984582cddb1936ec44bf2756f8a1 (patch) | |
tree | 8b2d2ec13c30c1dee1304ee52b713b26cd48f497 /arch/arm/cpu/arm720t | |
parent | c82014daf5ed8030d2ec5903bd51b5ab817fb000 (diff) | |
download | u-boot-imx-9399e540ca5b984582cddb1936ec44bf2756f8a1.zip u-boot-imx-9399e540ca5b984582cddb1936ec44bf2756f8a1.tar.gz u-boot-imx-9399e540ca5b984582cddb1936ec44bf2756f8a1.tar.bz2 |
ARM: tegra: amend pmc.h for Tegra114+
Tegra114 and later's PMC module removes the pwrgate_timer_on register
and replaces it with a clamp_status register. Adjust pmc.h to reflect
this, and update any code affected by the change.
The cpu.c change in this patch was extracted from a much larger patch
by Jimmy Zhang. The pmc.h change was written from scratch, but inspired
by related changes made by Tom Warren.
There could well be other differences in the PMC register set for chips
after Tegra20/30. However, they don't affect the code in U-Boot at
present, so I haven't attempted an exhaustive update of pmc.h.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Thierry Reding <treding@nvidia.com>
Acked-by: Thierry Reding <treding@nvidia.com>
Tested-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Diffstat (limited to 'arch/arm/cpu/arm720t')
-rw-r--r-- | arch/arm/cpu/arm720t/tegra114/cpu.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/arm/cpu/arm720t/tegra114/cpu.c b/arch/arm/cpu/arm720t/tegra114/cpu.c index 51ecff7..7a1747a 100644 --- a/arch/arm/cpu/arm720t/tegra114/cpu.c +++ b/arch/arm/cpu/arm720t/tegra114/cpu.c @@ -219,8 +219,8 @@ static int is_clamp_enabled(u32 mask) struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE; u32 reg; - /* Get clamp status. TODO: Add pmc_clamp_status alias to pmc.h */ - reg = readl(&pmc->pmc_pwrgate_timer_on); + /* Get clamp status. */ + reg = readl(&pmc->pmc_clamp_status); return (reg & mask) == mask; } |