arm: Remove support for s3c4510

This stuff has been rotting in the tree for a year now. Remove it.

Signed-off-by: Marek Vasut <marex@denx.de>

5 files changed, 2 insertions, 256 deletions

diff --git a/arch/arm/cpu/arm720t/cpu.c b/arch/arm/cpu/arm720t/cpu.c
index e25f6f2..864720f 100644
--- a/arch/arm/cpu/arm720t/cpu.c
+++ b/arch/arm/cpu/arm720t/cpu.c
@@ -46,7 +46,7 @@ int cleanup_before_linux (void)
 	 * and we set the CPU-speed to 73 MHz - see start.S for details
 	 */
 
-#if defined(CONFIG_NETARM) || defined(CONFIG_S3C4510B)
+#if defined(CONFIG_NETARM)
 	disable_interrupts ();
 	/* Nothing more needed */
 #elif defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_INTEGRATOR)
diff --git a/arch/arm/cpu/arm720t/interrupts.c b/arch/arm/cpu/arm720t/interrupts.c
index 5b21cc3..e3b59fe 100644
--- a/arch/arm/cpu/arm720t/interrupts.c
+++ b/arch/arm/cpu/arm720t/interrupts.c
@@ -45,28 +45,10 @@
 #define READ_TIMER (TM2STAT & NETARM_GEN_TSTAT_CTC_MASK)
 #endif
 
-#ifdef CONFIG_S3C4510B
-/* require interrupts for the S3C4510B */
-# ifndef CONFIG_USE_IRQ
-#  error CONFIG_USE_IRQ _must_ be defined when using CONFIG_S3C4510B
-# else
-static struct _irq_handler IRQ_HANDLER[N_IRQS];
-# endif
-#endif	/* CONFIG_S3C4510B */
-
 #ifdef CONFIG_USE_IRQ
 void do_irq (struct pt_regs *pt_regs)
 {
-#if defined(CONFIG_S3C4510B)
-	unsigned int pending;
-
-	while ( (pending = GET_REG( REG_INTOFFSET)) != 0x54) {  /* sentinal value for no pending interrutps */
-		IRQ_HANDLER[pending>>2].m_func( IRQ_HANDLER[pending>>2].m_data);
-
-		/* clear pending interrupt */
-		PUT_REG( REG_INTPEND, (1<<(pending>>2)));
-	}
-#elif defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_INTEGRATOR)
+#if defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_INTEGRATOR)
 	/* No do_irq() for IntegratorAP/CM720T as yet */
 #else
 #error do_irq() not defined for this CPU type
@@ -74,23 +56,6 @@ void do_irq (struct pt_regs *pt_regs)
 }
 #endif
 
-#ifdef CONFIG_S3C4510B
-static void default_isr( void *data) {
-	printf ("default_isr():  called for IRQ %d\n", (int)data);
-}
-
-static void timer_isr( void *data) {
-	unsigned int *pTime = (unsigned int *)data;
-
-	(*pTime)++;
-	if ( !(*pTime % (CONFIG_SYS_HZ/4))) {
-		/* toggle LED 0 */
-		PUT_REG( REG_IOPDATA, GET_REG(REG_IOPDATA) ^ 0x1);
-	}
-
-}
-#endif
-
 #if defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_INTEGRATOR)
 	/* Use IntegratorAP routines in board/integratorap.c */
 #else
@@ -98,32 +63,6 @@ static void timer_isr( void *data) {
 static ulong timestamp;
 static ulong lastdec;
 
-#if defined(CONFIG_USE_IRQ) && defined(CONFIG_S3C4510B)
-int arch_interrupt_init (void)
-{
-	int i;
-
-	/* install default interrupt handlers */
-	for ( i = 0; i < N_IRQS; i++) {
-		IRQ_HANDLER[i].m_data = (void *)i;
-		IRQ_HANDLER[i].m_func = default_isr;
-	}
-
-	/* configure interrupts for IRQ mode */
-	PUT_REG( REG_INTMODE, 0x0);
-	/* clear any pending interrupts */
-	PUT_REG( REG_INTPEND, 0x1FFFFF);
-
-	lastdec = 0;
-
-	/* install interrupt handler for timer */
-	IRQ_HANDLER[INT_TIMER0].m_data = (void *)&timestamp;
-	IRQ_HANDLER[INT_TIMER0].m_func = timer_isr;
-
-	return 0;
-}
-#endif
-
 int timer_init (void)
 {
 #if defined(CONFIG_NETARM)
@@ -137,29 +76,6 @@ int timer_init (void)
 
 	/* set timer 2 counter */
 	lastdec = TIMER_LOAD_VAL;
-#elif defined(CONFIG_S3C4510B)
-	/* configure free running timer 0 */
-	PUT_REG( REG_TMOD, 0x0);
-	/* Stop timer 0 */
-	CLR_REG( REG_TMOD, TM0_RUN);
-
-	/* Configure for interval mode */
-	CLR_REG( REG_TMOD, TM1_TOGGLE);
-
-	/*
-	 * Load Timer data register with count down value.
-	 * count_down_val = CONFIG_SYS_SYS_CLK_FREQ/CONFIG_SYS_HZ
-	 */
-	PUT_REG( REG_TDATA0, (CONFIG_SYS_SYS_CLK_FREQ / CONFIG_SYS_HZ));
-
-	/*
-	 * Enable global interrupt
-	 * Enable timer0 interrupt
-	 */
-	CLR_REG( REG_INTMASK, ((1<<INT_GLOBAL) | (1<<INT_TIMER0)));
-
-	/* Start timer */
-	SET_REG( REG_TMOD, TM0_RUN);
 #elif defined(CONFIG_TEGRA)
 	/* No timer routines for tegra as yet */
 	lastdec = 0;
@@ -237,26 +153,6 @@ void udelay_masked (unsigned long usec)
 	} while (diff >= 0);
 }
 
-#elif defined(CONFIG_S3C4510B)
-
-ulong get_timer (ulong base)
-{
-	return timestamp - base;
-}
-
-void __udelay (unsigned long usec)
-{
-	u32 ticks;
-
-	ticks = (usec * CONFIG_SYS_HZ) / 1000000;
-
-	ticks += get_timer (0);
-
-	while (get_timer (0) < ticks)
-		/*NOP*/;
-
-}
-
 #elif defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_INTEGRATOR)
 	/* No timer routines for IntegratorAP/CM720T as yet */
 #elif defined(CONFIG_TEGRA)
diff --git a/arch/arm/cpu/arm720t/s3c4510b/Makefile b/arch/arm/cpu/arm720t/s3c4510b/Makefile
deleted file mode 100644
index 5c6df08..0000000
--- a/arch/arm/cpu/arm720t/s3c4510b/Makefile
+++ /dev/null
@@ -1,45 +0,0 @@
-#
-# (C) Copyright 2000-2008
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(SOC).o
-
-COBJS-y	+= cache.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
-OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS-y))
-
-all:	$(obj).depend $(LIB)
-
-$(LIB):	$(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
diff --git a/arch/arm/cpu/arm720t/s3c4510b/cache.c b/arch/arm/cpu/arm720t/s3c4510b/cache.c
deleted file mode 100644
index 104d287..0000000
--- a/arch/arm/cpu/arm720t/s3c4510b/cache.c
+++ /dev/null
@@ -1,86 +0,0 @@
-/*
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Alex Zuepke <azu@sysgo.de>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <asm/hardware.h>
-
-void icache_enable (void)
-{
-	s32 i;
-
-	/* disable all cache bits */
-	CLR_REG( REG_SYSCFG, 0x3F);
-
-	/* 8KB cache, write enable */
-	SET_REG( REG_SYSCFG, CACHE_WRITE_BUFF | CACHE_MODE_01);
-
-	/* clear TAG RAM bits */
-	for ( i = 0; i < 256; i++)
-	  PUT_REG( CACHE_TAG_RAM + 4*i, 0x00000000);
-
-	/* clear SET0 RAM */
-	for(i=0; i < 1024; i++)
-	  PUT_REG( CACHE_SET0_RAM + 4*i, 0x00000000);
-
-	/* clear SET1 RAM */
-	for(i=0; i < 1024; i++)
-	  PUT_REG( CACHE_SET1_RAM + 4*i, 0x00000000);
-
-	/* enable cache */
-	SET_REG( REG_SYSCFG, CACHE_ENABLE);
-
-}
-
-void icache_disable (void)
-{
-	/* disable all cache bits */
-	CLR_REG( REG_SYSCFG, 0x3F);
-}
-
-int icache_status (void)
-{
-	return GET_REG( REG_SYSCFG) & CACHE_ENABLE;
-}
-
-void dcache_enable (void)
-{
-	/* we don't have seperate instruction/data caches */
-	icache_enable();
-}
-
-void dcache_disable (void)
-{
-	/* we don't have seperate instruction/data caches */
-	icache_disable();
-}
-
-int dcache_status (void)
-{
-	/* we don't have seperate instruction/data caches */
-	return icache_status();
-}
diff --git a/arch/arm/cpu/arm720t/start.S b/arch/arm/cpu/arm720t/start.S
index 0daf848..3a90e0d 100644
--- a/arch/arm/cpu/arm720t/start.S
+++ b/arch/arm/cpu/arm720t/start.S
@@ -335,22 +335,6 @@ cpu_init_crit:
 	ldr	r0, =NETARM_GEN_MODULE_BASE
 	str	r1, [r0, #+NETARM_GEN_INTR_ENABLE]
 
-#elif defined(CONFIG_S3C4510B)
-
-	/*
-	 * Mask off all IRQ sources
-	 */
-	ldr	r1, =REG_INTMASK
-	ldr	r0, =0x3FFFFF
-	str	r0, [r1]
-
-	/*
-	 * Disable Cache
-	 */
-	ldr r0, =REG_SYSCFG
-	ldr r1, =0x83ffffa0	/* cache-disabled  */
-	str r1, [r0]
-
 #elif defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_INTEGRATOR)
 	/* No specific initialisation for IntegratorAP/CM720T as yet */
 #elif defined(CONFIG_TEGRA)
@@ -569,9 +553,6 @@ reset_cpu:
 	ldr	r1, =NETARM_GEN_SW_SVC_RESETB
 	str	r1, [r4, #+NETARM_GEN_SOFTWARE_SERVICE]
 	mov	pc, r0
-#elif defined(CONFIG_S3C4510B)
-/* Nothing done here as reseting the CPU is board specific, depending
- * on external peripherals such as watchdog timers, etc. */
 #elif defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_INTEGRATOR)
 	/* No specific reset actions for IntegratorAP/CM720T as yet */
 #elif defined(CONFIG_TEGRA)